Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-02-11
2001-05-29
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189020, C365S220000, C365S226000, C365S227000, C365S189050, C365S230030, C365S230080
Reexamination Certificate
active
06240046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to architecture and organization of a random-access memory array having lower power consumption read operations.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
The need for ever-increasing memory performance at reasonable cost continues unabated. It is being driven by numerous advances toward higher frequency and higher speed applications. For example, the increasing bandwidth demands of computer networking and the internet, the increasing speeds of commercially available processors, and the proliferation of high-frequency wireless communication systems are all driving the need for higher performance memory subsystems.
In addition to the increased speed requirements of memory systems, there is also an increasing need for memory with reduced power consumption. Many prior art memories have a data bus that is one word wide coupled to a memory array. Such circuits perform a read cycle each time a read request occurs. Other prior art memories have a data bus that is two data words wide coupled to a memory array. In a read cycle, the memory retrieves both data words and outputs a first data word (the requested data word) in response to the read request. If the second data word is requested in the next read cycle, then the second data word is presented in response to the second read request with no activity required of the memory array. Otherwise, the second data word is discarded. Many memory devices are utilized in environments that require low power usage (e.g. portable computing systems). Therefore, there is an unfilled need for memory devices with low power consumption characteristics.
SUMMARY OF THE INVENTION
In accordance with the present invention, a random access memory integrated circuit having statistically lower average power consumption is presented. The memory includes a memory array capable of storing a plurality of data words and a data bus having a width of more than one data word coupled to the memory array. The memory is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle.
Some embodiments further include a burst mode of operation which provides, during subsequent read cycles, read access to sequential addressed memory cells relative to a received (i.e., “load”) address, without requiring such sequential addresses be presented to the device. For example, using a 72-bit wide (double word) organization of each memory bank, two 36-bit words can be retrieved from the memory array in the first cycle. The second word can be saved to present to the data outputs after the first word is output. Because this embodiment is organized into separate memory banks, a burst of four sequential words may transcend the address boundaries between memory banks. Consequently, the embodiments of the memory array include provision for automatically initiating a load cycle in another memory bank during a burst cycle.
Additionally, some embodiments can include a flip-flop having a first state and a second state. In the first state, the integrated circuit retrieves one word of data in a single clock cycle and in the second state the integrated circuit retrieves more than one data word from the memory array in the single clock cycle. Therefore, if the flip-flop is in the first state the integrated circuit retrieves only the addressed data word from the memory array in a clock cycle, the addressed data word being read from the integrated circuit in response to a read request. If the flip-flop is in the second state, the integrated circuit retrieves more than one data word, the addressed data word being one of the data words retrieved. The addressed data word is read from the integrated circuit in response to the first read request and the remaining data words are stored in order to respond to “continue the present burst” read requests.
Significant power savings can occur if the flip-flop is appropriately set for the prevalent operation of the integrated circuit. If the data words that are stored in the memory array are randomly accessed, then power can be conserved by retrieving one data word in a clock cycle from the memory array compared to the power used to retrieve multiple words and output only one of them. However, if all or most read cycles are burst read cycles (i.e., a number of sequential read operations immediately following a random “load read” cycle in sequential clock cycles), then significant power savings can be realized if more than one data words are retrieved from the memory array in each clock cycle during which data is retrieved from the memory array.
For example, if the data bus is two (36-bit) words wide then the power required to retrieve two words in a clock cycle is about 20% higher than the power required to retrieve one word in a clock cycle. Therefore, the power usage for retrieving two data words in a clock cycle that accesses the memory array is 120% that required to retrieve a single data word in a clock cycle that accesses the memory array. There is no additional power expenditure if the memory array is not accessed. If the read cycles are random read cycles then there is a 20% increase in power usage for retrieving both data words on each clock cycle that accesses the memory array instead of retrieving a single data word each clock cycle. Therefore, power can be saved by only retrieving a single data word on each clock cycle.
However, if the read cycles are burst cycles, and the second data word as well as the first data word are retrieved in response to the “load read” cycle, then there is a significant decrease in average power usage for retrieving two data words in each clock cycle that the memory array is accessed. Although each cycle two data words are retrieved there is an expenditure of 120% the power used in one cycle when retrieving only a single data word, the memory array is only accessed half as many times. Therefore, there is an overall average expenditure of power that is only 60% the power usage of retrieving a single data word in each cycle.
In some embodiments of the invention, the flip-flop is in the first state when the integrated circuit is first powered up. The flip-flop is set to the second state the first time that a read request is presented in a first clock cycle followed by an advance (“continue the present burst”) control signal on
Integrated Device Technology Inc.
Skjerven Morrill MacPherson Franklin & Friel
Tran Andrew Q.
LandOfFree
Integrated circuit random access memory capable of reading... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit random access memory capable of reading..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit random access memory capable of reading... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2467333