Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection
Reexamination Certificate
1999-08-02
2001-04-10
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Device protection
C257S355000, C361S056000
Reexamination Certificate
active
06215135
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an integrated circuit comprising protection means for protecting against electrostatic discharge, which protection means is provided on a substrate of a first conductivity type, and said protection means comprises a first highly doped surface area of a second, opposite, conductivity type, a second highly doped surface area of the second conductivity type, a first gate insulated from the surface of the integrated circuit, which first gate is positioned so as to form a first MOS-device in conjunction with the first and the second highly doped surface areas, and a third highly doped surface area of the first conductivity type, which is located directly beside the second highly doped surface area, the first gate and the second and the third highly doped surface areas are electrically coupled to a first reference terminal, the substrate being provided with a well of the second conductivity type, the well being partly stretched out into the region of the first highly doped surface area, and the well being provided with a fourth highly doped surface area of the first conductivity type which is electrically coupled to a bonding pad BP of the integrated circuit.
Such an integrated circuit is known from the general state of the art. The fourth highly doped surface area, the well, the substrate, and the second highly doped surface area together form an SCR element (Silicon-Controlled Rectifier). The SCR element is in fact a four-layer pnpn (or npnp) structure with connections on the outer p-layer and the outer n-layer. One of the connections is formed by the fourth highly doped surface area and the other one of the connections is formed by the second highly doped surface area. A purpose of the protection means is to avoid damage in the integrated circuit caused by electrostatic discharge (ESD). In general, diodes, Field oxide NMOS, thin oxide NMOS, and Silicon Controlled Rectifiers are used as ESD protection means.
A problem of the known ESD protection means is that if for instance the bonding pad is negatively biased with respect to the first reference terminal, no n
+
diffusion is to be electrically connected to the bonding pad in a p-substrate CMOS integrated circuit, because the n
+
diffusion at the bonding-pad would be forward biased with respect to the substrate. This would cause a current through the substrate, which adversely affects the behaviour of the integrated circuit. For the same reason, an n
+
/p diode and an NMOS as ESD protection means coupled to the first reference terminal is not allowed.
SUMMARY OF THE INVENTION
It is an object of the invention to solve the above-mentioned problem.
An inventive integrated circuit of the type described in the opening paragraph is therefore characterized in that the well further comprises a fifth highly doped surface area of the first conductivity type, a second gate insulated from the surface of the integrated circuit, and a sixth highly doped surface area of the second conductivity type which is located directly beside the fifth highly doped surface area, and in that the second gate is positioned so as to form a second MOS-device in conjunction with the fourth and the fifth highly doped surface areas, and in that the second gate and the fifth and the sixth highly doped surface areas are electrically coupled to a second reference terminal. As a result, the protection means provide for two protection paths. Let us for example assume that the first conductivity type is the p-type and the second conductivity type is the n-type. Then one of the two protection paths, hereinafter referred to as first protection path, comprises a p
+
n diode, which is formed by the p
+
diffusion (the fourth highly doped surface area) at the bonding pad and the n-well (i.e. the well if the second conductivity type is the n-type). Thus, the first protection path forms an ESD-protection between the bonding pad and the second reference terminal. The other one of the two protection paths, hereinafter referred to as the second protection path, is formed by the SCR of which, in this example, the outer p-layer is formed by the fourth p
+
doped surface area in the n-well, and of which the outer n-layer is formed by the second n
+
doped surface area in the p-type substrate. In this example, in which the first conductivity type is the p-type and the second conductivity type is the n-type, the protection means according to the invention do not have an n
+
diffusion which is electrically connected to the bonding-pad. This is in contrast with the known protection means.
REFERENCES:
patent: 5400202 (1995-03-01), Metz et al.
patent: 5576557 (1996-11-01), Ker et al.
patent: 5615073 (1997-03-01), Fried et al.
patent: 5739998 (1998-04-01), Wada
patent: 6081002 (2000-06-01), Amerasekera et al.
patent: 0774785A2 (1997-05-01), None
Biren Steven R.
Mintel William
Nadav Ori
U.S. Philips Corporation
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