Integrated circuit provided with a protection against...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S058000, C361S111000

Reexamination Certificate

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06882512

ABSTRACT:
An integrated circuit including an output pad, an output block coupled to the output pad via a capacitor, a first one-way conduction element for connecting the pad to a supply line when the voltage on the pad exceeds the voltage of the supply line by a first threshold voltage, a second one-way conduction element for connecting the pad to the circuit ground when the voltage on the pad is smaller than the ground voltage by a second threshold voltage, a resistor coupled on the one hand to the output pad and on the other hand to the supply line via a switch which is turned off when the circuit is idle and which is turned on when the circuit is in a normal operating mode.

REFERENCES:
patent: 3603865 (1971-09-01), Liebenthal
patent: 4858055 (1989-08-01), Okitaka
patent: 5005061 (1991-04-01), Robb et al.
patent: 5086365 (1992-02-01), Lien
patent: 5534810 (1996-07-01), White
patent: 5631793 (1997-05-01), Ker et al.
patent: 5654862 (1997-08-01), Worley et al.
French Search Report from French Patent Application 00/11075, filed Aug. 30, 2000.
Mack W.D., et al, “New ESD Protection Schemes For BICMOS Processes With Application To Cellular Radio Designs” San Diego, May 10-13, 1992, New York, IEEE, US, vol. CONF. 25, May 10, 1992.

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