Integrated circuit protected against electrostatic...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive

Reissue Patent

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C361S056000, C361S091200, C257S356000

Reissue Patent

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RE037477

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns integrated circuits made with MOS (metal-oxide-semiconductor) technology and, more generally, integrated circuits susceptible to risks of malfunctioning or destruction in the presence of electrostatic discharges.
Electrostatic discharges may sometimes occur quite simply because a user touches the input/output terminals of the integrated circuits. This risk will become increasingly frequent as integrated circuits come into widespread use among the public, for example in the form of chip cards which will undergo a lot of handling and in which the output terminal can be directly accessed without protection.
2. Description of the Prior Art
To protect integrated circuits against these risks, it is now standard practice to provide for an element integrated in the circuit, between each of the signal terminals and the common ground terminal. The function of this element is to become suddenly conductive when overvoltage, exceeding a pre-defined threshold, appears between its terminals. This element, of course, has energy absorption or current absorption capacities which are greater than those of the other elements of the integrated circuit and, furthermore, it is designed to become conductive more quickly than the elements to be protected in the integrated circuit.
In a standard way, the protection element is a diode with its anode connected to the ground terminal and its cathode connected to another input/output terminal (assuming, of course, that the ground terminal is a negative supply terminal).
This diode stays normally off for as long as the voltage of the terminal to be protected does not go beyond an avalanche threshold. If the threshold is exceeded, the diode goes into avalanche mode and absorbs the electrostatic discharge current. It must go into avalanche mode before the other junctions, present in the integrated circuit and subject to the same overvoltage. Now, the voltage for triggering the avalanche process is essentially related to technological parameters such as the doping of the semiconducting substrate in which the circuit is formed, and the doping of the various regions diffused in this substrate.
It is difficult to have precise knowledge of the avalanche voltages of the junctions to be protected and to master the making of a protective diode with an avalanche voltage which would be below that of the junctions to be protected while, at the same time, remaining greater than the normal operating voltages of the circuit. For, it would be unacceptable for the protection element to go into a conduction state simply because a signal which has a relatively wide amplitude (but does not represent a dangerous discharge) appears at a terminal of the circuit.
Now, the specifications relating to behaviour, under voltage, of the integrated circuits are relatively strict and are finally fairly close to voltages which might damage or destroy the circuit. For example, specifications may require that the circuit should work normally if it receives signals or supply voltages of up to 15 volts, whereas the destruction threshold would be 22 volts. It must therefore be seen to it that the triggering of the protective element starts from a voltage which is considerably below 22 volts (if it is too close to 22 volts, there remains a risk of destruction because the conduction is not triggered fast enough). But it is also necessary that the protection element should be triggered for a voltage which is sufficiently greater than 15 volts (if not, there is a risk of untimely triggering below 15 volts).
The margin available for choosing the avalanche voltage is therefore narrow and it is all the smaller as technological variations are greater, i.e. it is all the smaller as the dimensions, concentrations, depths of junctions and other parameters are less well controlled in the manufacturing process.
To arrive at protection of the integrated circuits which is as efficient as possible while, at the same time, permitting normal functioning voltages which are as high as possible, the present invention proposes a new approach based on the observation that the rising edge of the overvoltages coming from electrostatic discharges (or of most overvoltages liable to appear and damage the circuits) is far steeper than the rising edge of the normal voltages (which may be relatively high) occurring at the input/output terminals of the circuit.
For, these normal voltages are either supply voltages which may exceed the value stipulated by the specifications but for which there is no reason or possibility that they should vary abruptly, or input-output logic signals which would exceptionally change to a value greater than the maximum permitted by the specifications. The rising edges of these logic signals do not exceed a few volts per nanosecond, while the rising edges of the electrostatic discharges rather have values of a some hundreds of volts per nanosecond.
SUMMARY OF THE INVENTION
According to the invention, it is proposed to connect, between two terminals of the integrated circuit, a diode associated with a means to modify the distribution of the equipotential lines at the position where the avalanche conduction of the diode is triggered, said means being connected to the terminal to be protected and being sensitive to the rising slope of the overvoltages appearing at this terminal in such a way that the avalanche triggering voltage is weaker, when the slope is steeper, than it is when the slope is less steep.
The means for modifying the distribution of equipotential lines is preferably an insulated gate surrounding an entire diffused region constituting the cathode (or anode) of the diode, and located in the immediate vicinity of this region.
This gate is connected to the terminal to be protected by an integrating circuit that introduces a time constant in such a way that an overvoltage with a steep edge reaching this terminal is transmitted with a slight delay to the gate.
For example, the gate is connected, firstly, to one end of a resistor, the other end of which is connected to the diffused region and the terminal to be protected and, secondly, to an end of a capacitor, the other end of which is connected to the other terminal of the diode.
In practice, the capacitor does not need to be given the form of a well identified circuit element, for the junction capacitances of the resistor (made by a diffused region in the substrate) and the capacitance between the gate and the semiconducting substrate in which the cathode of the diode is diffused are high enough to play the role expected of them, namely to cause a delay in the arrival of a voltage front at the gate. This delay induces a potential difference between the diffused region and the gate, which is all the greater as the front is steeper.


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IBM Technical Disclosure Bulletin, vol. 23, No. 2, Jul. 1980.*
IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1985.*
IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985.*
1987 IEEE “How to Prevent Circuit Zapping” Robert J. Antinone, BDM Corporation, pp. 34-38.
Textbook Discussion of ESD, “VLSI Engineering,” Prentice Hall, 1988, Thomas E. Dillinger, pp. 508-511.
1988 IEEE/IRPS, “Failure in CMOS Circuits Induced by Hot Carriers in Multi-gate Transistors,” A. Chatterjee, et al., pp. 26-28.
1988 IEEE/IRPS “Internal Chip ESD Phenomena Beyond the Protection Circuit,” V. Duvvery, et al., pp. 19-25.

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