Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-12-29
2002-03-26
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S296000, C438S585000, C438S719000, C438S926000, C438S221000
Reexamination Certificate
active
06362074
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuit fabrication and in particular the present invention relates to improving gate electrode fabrication by reducing etch byproducts contributed by shallow trench region features.
BACKGROUND
Integrated circuits contain thousands, if not millions, of individual structures fabricated on individual die which are fabricated on a common wafer. The dies are subsequently separated during processing. The structures fabricated on each individual integrated circuit die are located across the die as dictated by their relationship to other structures on the die. That is, two circuit structures which are connected electrically will preferably be located in relative proximity to each other. It will be appreciated, that physical open areas will exist between some structures when a layout of the integrated circuit to die is complete. To maintain a uniform density across the die, and the integrated circuit wafer, dummy structures, such as dummy active areas and dummy polysilicon lines, can be placed in the open areas. These dummy structures are not operative, but provide benefits during processing. For example, dummy structures can be located throughout an integrated circuit to improve planarization during chemical mechanical polishing (CMP) of subsequent dielectric layers. These structures are important to help maintain a uniform pressure across the wafer during CMP processing. During subsequent fabrication operations, the dummy structures are typically ignored.
Many operations performed while fabricating an integrated circuit depend upon variables measured during fabrication. One such operation is a bulk etch process performed on a layer of polysilicon used to fabricate transistor gates. The etch process removes undesired polysilicon, but can remove gate oxide located beneath the polysilicon layer. To fully remove the undesired polysilicon, without removing gate oxide, a byproduct of the etching process is chemically monitored to determine when the gate oxide is reached. Thus, a clear chemical transition is desired to be provided to improve the end point of the polysilicon etch. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved polysilicon etch process which has a clear end point.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuit fabrication and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In particular, one embodiment of the present invention describes an integrated circuit comprising shallow trench region features formed of an insulator material, gate oxide regions, and polysilicon regions located on top of the gate oxide regions and the shallow trench region features. The polysilicon regions are formed from a layer of polysilicon which has been etched to form transistor gate electrodes on top of the gate oxide regions and form the polysilicon over the shallow trench region features.
In another embodiment, a method of forming transistor gate electrodes is described. The method comprises fabricating shallow trench region features in a substrate, fabricating a layer of gate oxide over the substrate, fabricating a layer of polysilicon over the layer of gate oxide, and selectively removing portions of the layer of polysilicon. Portions of the polysilicon material remain over the layer of gate oxide to form the transistor gate electrodes, and polysilicon material remains over the shallow trench region features.
In yet another embodiment, a method of fabricating an integrated circuit is provided. The method comprises fabricating a plurality of shallow trench region features in a substrate, fabricating a layer of oxide over the substrate, and fabricating a layer of polysilicon over the layer of oxide and the plurality of shallow trench region features. The method also comprises selectively etching portions of the layer of polysilicon such that polysilicon material remains over the plurality of shallow trench region features, monitoring byproducts during the etch, and terminating the etch based upon a composition of the byproducts during the etch.
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Wolf, S. et al., Silicon Processing For The VLSI Era, vol. 1, Wolf, 1986 by Lattice Press, pp. 565-568.
Estrada Michelle
Fourson George
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
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