Integrated circuit power-up controllers, integrated circuit...

Details Integrated circuit power-up controllers, integrated circuit... Integrated circuit power-up controllers, integrated circuit...

1999-03-08

2001-03-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Powering

C365S189070, C365S189110

Reexamination Certificate

active

06201751

ABSTRACT:

TECHNICAL FIELD
This invention relates to integrated circuit power-up controllers, to integrated circuit power-up circuits, and to integrated circuit power-up methods. The invention is particularly useful in the context of double data rate (DDR) synchronous dynamic random access memory (DRAM) devices.
BACKGROUND OF THE INVENTION
Integrated circuit devices must typically be powered up when operation is initiated. During power-up of an integrated circuit, certain operational parameters must generally be maintained and managed if the integrated circuit is to operate properly after power-up. Power-up can typically involve application of a voltage V
DD
to the circuit.
One special type of circuit is a double data rate (DDR) synchronous DRAM. Synchronous DRAMs are described generally in U.S. Pat. Nos. 5,751,656, 5,749,086, 5,666,321, and 5,544,124, assigned to the assignee of this disclosure, and incorporated by reference herein. Typically with such devices, it is desirable to maintain the control pin CKE at a first value during application of a voltage, V
DD
, to the circuit. After the circuit has stabilized, and a number of conditions have been met for a period of time, typically 200 microseconds, then CKE must be taken to an input above its first value (e.g. 2 volts). If CKE is taken to an input above its first value prior to the allotted time, circuit operations downstream of power-up can be affected.
One typical prior art way of achieving a desired delay before moving CKE to its desired input, is illustrated by the high level circuit diagram shown in
FIG. 1
generally at
20
. Circuit
20
includes a delay network
22
. Delay network
22
, in the past, has comprised first and second RC networks
24
,
26
, respectively. Essentially, delay network
22
powers-up in accordance with a predetermined delay which is appropriate for enabling certain conditions to be met, e.g. stable power, stable clock, and no operation conditions. A CKE input buffer
28
is provided whose output, CKE, can be taken to its desired voltage after the delay of delay network
22
has been achieved. There are, however, problems associated with the use of a delay network such as delay network
22
. Such networks can be unpredictable insofar as performance of the individual RC networks
24
,
26
, respectively. Specifically, if the delay, for whatever reason, is not adequately long enough, then power-up can be prematurely set off which has downstream implications insofar as circuit operation is concerned.
Accordingly, this invention arose out of concerns associated with providing improved power-up controllers and circuitry, as well as improved power-up methods for integrated circuitry. In particular, this invention arose out of concerns associated with providing improved power-up controllers and circuitry, as well as improved power-up methods for use in connection with dynamic random access memory circuitry.
SUMMARY OF THE INVENTION
Integrated circuit power-up controllers, integrated circuit power-up circuits, and integrated circuit power-up methods are described. In one embodiment, first and second circuits are provided each having their own outputs. A state-dependent, power-up control circuit includes two inputs which are coupled respectively with the outputs of the first and second circuits. The state-dependent, power-up control circuit is configured to initiate power-up of a desired circuit after a predetermined state has been achieved at the two inputs. In another embodiment, a delay circuit is provided and configured to provide a delayed output. An input circuit is provided having an output. A power-up control circuit has inputs which are coupled respectively with the outputs of the delay circuit and the input circuit. The power-up control circuit has an output line which can assume a plurality of power-up states. A feedback control loop is operatively connected with the power-up control circuit output line and the input circuit for controlling operational aspects of the input circuit responsive to power-up states achieved by the power-up control circuit. In a preferred embodiment, logic circuitry is provided for controlling the power-up states of the power-up circuit.


REFERENCES:
patent: 4901283 (1990-02-01), Hanbury et al.
patent: 5517137 (1996-05-01), Stephens, Jr.
patent: 5544124 (1996-08-01), Zagar et al.
patent: 5557579 (1996-09-01), Raad et al.
patent: 5586077 (1996-12-01), Olivio et al.
patent: 5666321 (1997-09-01), Schaefer
patent: 5749086 (1998-05-01), Ryan
patent: 5751656 (1998-05-01), Schaefer
patent: 5889719 (1999-03-01), Yoo et al.
patent: 5898635 (1999-04-01), Raad et al.
patent: 5986959 (1999-11-01), Itou

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