Integrated circuit power device with external disabling of defec

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

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257341, 257368, 257379, 257431, H01L 2348

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active

054463106

ABSTRACT:
An integrated circuit power device includes many cell blocks which are electrically connected in parallel, with each of the cell blocks including at least one cell such as MOSFET, electrically connected in parallel. External measurement access means such as test pads are electrically connected to each cell block, so that the cell blocks can be externally measured and a defective cell block can be identified. Externally activated disabling means such as fusible links are also provided, so that the fusible links connected to defective cell blocks can be opened. An operable integrated circuit power device is thereby obtained, notwithstanding a defective cell block. The fusible links are incapable of automatic activation in response to the defect in the cell block, but are externally opened upon detection of a defective cell block. By decoupling the defect measurement and cell disabling functions, low levels of leakage current may be specified for the power device. The fusible links are preferably formed using the same mask and material as the gate electrode, so that extra fabrication steps are not needed.

REFERENCES:
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patent: 4786958 (1988-11-01), Bhagat
patent: 4942308 (1990-07-01), Conzelmann et al.
patent: 4975782 (1990-12-01), Bauer
patent: 5021861 (1991-06-01), Baliga
patent: 5025298 (1991-06-01), Fay et al.
patent: 5097448 (1992-03-01), Segawa
patent: 5100829 (1992-03-01), Fay et al.
A Large Area MOS-GTO with Wafer-Repair Technique, M. Stoisiek et al., IEDM, 1987, pp. 666-669.
Modern Power Devices, B. Jayant Baliga, John Wiley & Sons, 1987, pp. 263-343.

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