Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal coating
Reexamination Certificate
1999-09-30
2004-03-23
Nicolas, Wesley A. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal coating
C205S293000, C205S296000, C205S298000
Reexamination Certificate
active
06709564
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention is concerned with copper plating for the metallization of integrated circuits (ICs).
The electronics industry is in the process of transitioning from aluminum to copper as the basic metallization for semiconductor IC's. The higher electrical conductivity of copper reduces resistive losses and enables the faster switching needed for future generations of advanced devices. Copper also has a higher resistance to electromigration than aluminum. The leading technology for fabricating copper circuitry on semiconductor chips is the “Damascene” process (see, e.g., P. C. Andricacos, Electrochem. Soc. Interface, Spring 1999, p.32; U.S. Pat. No 4,789,648 to Chow et al.; U.S. Pat. No 5,209,817 to Ahmad et al.). Under this process, vias are etched through and trenches are etched in the chip's dielectric material, which is typically silicon dioxide, although materials with lower dielectric constants are desirable. A barrier layer, e.g., titanium nitride (TiN) or tantalum nitride (TaN), is deposited into the trenches and vias by reactive sputtering, to prevent Cu migration into the dielectric material and degradation of the device performance. A thin sputtered copper seed layer is deposited next, to facilitate copper electrodeposition. Copper is then electrodeposited into the trenches and vias. Copper deposited on the outer surface, i.e., outside of the trenches and vias, is removed by chemical mechanical polishing (CMP). The “dual Damascene” process involves deposition in both trenches and vias at the same time.
Electrodepositing copper into trenches and vias as required by the Damascene process has proven to be difficult, particularly with respect to the bottom-up filling of small features which are often submicron in size. Until now, copper electrodeposition efforts have focused on adopting the acid copper sulfate plating system currently used for most circuit board plating. However, acid copper sulfate baths have significant disadvantages for chip plating. A major disadvantage is that the sulfate anions used in acid copper sulfate systems do not complex copper ions very well. This allows the copper to plate out at a low voltage, which, unless suppressed, can result in runaway deposition that can lead to powdery or nodular deposits. To prevent this while providing the leveling power needed for bottom-up filling of the chip features, a relatively complicated additive system with at least two additive components is required. One essential component, the suppressor, is typically a polymeric organic species, e.g., high molecular weight polyethylene glycol, that adsorbs strongly on the copper electrode surface, forming a film which sharply suppresses the deposition rate. The other essential acid copper sulfate additive component, the anti-suppressor, counters this suppressive effect to provide the mass-transport-limited rate differential needed for leveling and bottom-up filling of the chip features. Note that additive species typically are present in small concentrations and are consumed during the metal electrodeposition process, so that they become depleted at the cathode surface unless they are replenished by vigorous solution agitation. Ideally, depletion of suppressor additive species results in faster metal deposition within trenches and vias, where solution agitation is less effective. For the acid copper sulfate system, however, a delicate balance between the effects of the two types of additive components must be maintained for consistent results. This is further complicated by the involvement of other species in the leveling process of practical acid copper sulfate systems.
Proprietary acid copper sulfate baths presently in use typically contain chloride ion and involve two additive component solutions, at least one of which contains more than one compound. A recent study (J. J. Kelly, C. Tian, and A. C. West, J. Electrochem. Soc. 146 (7) (1999), p. 2540) showed that adequate leveling occurs only when all four constituents of a model additive system (chloride, polyethylene glycol suppressor, and two anti-suppressing compounds) were present. The difficulty of adequately controlling the concentrations of the various additive species (and of taking into account additive-additive interactions) limits the efficacy of acid copper sulfate for uniform plating of high aspect ratio features.
Another disadvantage of acid copper sulfate systems is that they provide relatively soft deposits having mechanical properties which are highly dependent on the substrate (i.e., the barrier and seed layer materials) (R. Haak, C. Ogden, and D. Tench, Plating Surf. Fin. 68 (10) (1981), p. 59; K. Abe, Y. Harada, and H. Onoda, IEEE 98CH36173 Ann. Int. Rel. Phys. Symp. (1998), p. 342), and which change with time at room temperature. Changing properties make it difficult to control the CMP process used to remove excess copper and planarize the wafer in the Damascene fabrication process. In addition, polishing tends to recess (“dish”) the soft copper in relatively wide trenches and bond pads, so that the planarity needed to facilitate bonding and minimize circuit electrical resistance is lost. Soft copper also tends to exacerbate CMP erosion of copper and dielectric material in clusters of closely-spaced narrow trenches.
SUMMARY OF THE INVENTION
A type of electrolytic solution for electroplating copper circuitry in trenches and vias of IC's is presented which overcomes the problems noted above. This type of solution provides good deposits even without organic additives, and requires only one organic additive species to provide outstanding leveling.
The invention described herein replaces the acid copper sulfate system currently used in the Damascene process with a plating system based on the use of highly complexing anions (e.g., pyrophosphate, cyanide, sulfamate, etc.) to provide an inherently high overvoltage that effectively suppresses runaway copper deposition. With the deposition naturally suppressed by an intrinsic electrolyte component that is in high concentration and is not depleted during the metal deposition process, the system requires only one organic additive species to provide the rate differential needed for good filling of chip features. Use of a single organic species greatly simplifies control of the additive concentration, and should permit bottom-up filling of Damascene trenches and vias having higher aspect ratios than can be filled with acid copper sulfate baths. In addition, highly complexed baths produce fine-grained copper deposits that are typically much harder than the large-grained acid sulfate copper deposits, and which exhibit stable mechanical properties that do not change with time, thereby minimizing “dishing” and giving more consistent CMP results. The mechanical properties and texture of the fine-grained deposits are also much less substrate dependent, which minimizes the effects of variations and flaws in the barrier and seed layers.
The preferred highly complexed bath for plating circuitry on semiconductor chips is copper pyrophosphate. The addition of a single organic compound (e.g., 2,5-dimercapto-1,3,4-thiadiazole) to the bath provides exceptional throwing power for plating high aspect ratio features. The copper deposits that result from a pyrophosphate bath with one organic additive are extremely fine-grained and typically about twice as hard as acid sulfate copper deposits, and exhibit little or no substrate dependence. The resistivity of pyrophosphate and annealed acid sulfate copper deposits are equivalent.
DESCRIPTION OF THE INVENTION
The Damascene process involves etching trenches and vias into IC dielectric layers, which, when filled with copper, become the chip's interconnecting circuitry. The present invention provides a plating system for the electrodeposition of copper into the trenches and vias (referred to herein as chip “features”). This plating system is based on the use of anions which complex copper ions well, such as pyrophosphate, cyanide, and sulfamate. Complexing the copper ions via an in
Brongo Maureen
Dornisch Dieter
Tench D. Morgan
White John T.
Koppel, Jacobs Patrick & Heybl
Nicolas Wesley A.
Rockwell Scientific Licensing LLC
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