Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2011-01-04
2011-01-04
Chambliss, Alonzo (Department: 2892)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S127000, C029S874000, C257S669000, C257S670000, C257S676000, C257S692000, C257SE23031, C257SE23043, C257SE23045, C361S813000
Reexamination Certificate
active
07863108
ABSTRACT:
A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
REFERENCES:
patent: 6380048 (2002-04-01), Boon et al.
patent: 6433424 (2002-08-01), Sammon
patent: 6437427 (2002-08-01), Choi
patent: 6525406 (2003-02-01), Chung et al.
patent: 6627977 (2003-09-01), Foster
patent: 6630373 (2003-10-01), Punzalan et al.
patent: 6713322 (2004-03-01), Lee
patent: 6713849 (2004-03-01), Hasebe et al.
patent: 6825062 (2004-11-01), Yee et al.
patent: 6828659 (2004-12-01), Iwakiri
patent: 6853059 (2005-02-01), Jang
patent: 6876069 (2005-04-01), Punzalan et al.
patent: 6995460 (2006-02-01), McLellan et al.
patent: 7049683 (2006-05-01), Sirinorakul et al.
patent: 7230323 (2007-06-01), Lee et al.
patent: 7242077 (2007-07-01), Ma et al.
patent: 7556987 (2009-07-01), Dimaano et al.
patent: 2001/0035569 (2001-11-01), Shibata
patent: 2004/0061204 (2004-04-01), Han et al.
patent: 2004/0061205 (2004-04-01), Han et al.
patent: 2004/0070056 (2004-04-01), Matsuzawa et al.
patent: 2005/0253230 (2005-11-01), Punzalan et al.
patent: 2005/0263861 (2005-12-01), Ahn et al.
patent: 2007/0235854 (2007-10-01), Camacho et al.
patent: 2007/0278633 (2007-12-01), Uematsu
patent: 2008/0001263 (2008-01-01), Dimaano et al.
patent: 05-243446 (1993-09-01), None
patent: 07-058143 (1995-03-01), None
Dimaano Jr. Antonio B.
Magno Sheila Rima C.
Shim Il Kwon
Chambliss Alonzo
Ishimaru Mikio
Stats Chippac Ltd.
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