Integrated circuit packaging system with a tiered substrate...

Details Integrated circuit packaging system with a tiered substrate... Integrated circuit packaging system with a tiered substrate...

2011-01-04

2011-01-04

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S686000, C257S778000

Reexamination Certificate

active

07863735

ABSTRACT:
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a tiered encapsulant above the base substrate, the tiered encapsulant having a first cavity above the base substrate and a second cavity above the first cavity adjacent an intermediate horizontal side; connecting an intermediate interconnect to the base substrate, the intermediate interconnect surrounded by the tiered encapsulant and substantially exposed on the intermediate horizontal side; and connecting a top interconnect to the base substrate, the top interconnect surrounded by the tiered encapsulant and substantially exposed on a top horizontal side.

REFERENCES:
patent: 7102892 (2006-09-01), Kledzik et al.
patent: 7598617 (2009-10-01), Lee et al.
patent: 2007/0235215 (2007-10-01), Bathan et al.
U.S. Appl. No. 12/192,052, filed Aug. 14, 2008, Park et al.

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