Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor
Patent
1986-09-26
1989-09-12
Macon, Robert S.
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific current responsive fault sensor
357 45, 357 55, 357 75, 357 80, 361400, 361412, 361414, 29832, 174 685, H01L 2302
Patent
active
048665088
ABSTRACT:
The present invention employs a high density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns. All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.
REFERENCES:
patent: 3290756 (1966-12-01), Dreyer
patent: 3679941 (1972-07-01), LaCombe et al.
patent: 3691628 (1972-09-01), Kim et al.
patent: 3702025 (1972-11-01), Archer
patent: 4300153 (1981-11-01), Ilayakawa et al.
patent: 4347306 (1982-08-01), Takeda et al.
patent: 4417393 (1983-11-01), Becker
patent: 4426773 (1984-01-01), Hargis
patent: 4588468 (1986-05-01), McGinty et al.
patent: 4613891 (1986-09-01), Ng et al.
patent: 4617085 (1986-10-01), Cole et al.
patent: 4677528 (1967-06-01), Miniet
Jubb, Charles "PC Board Layout Via AutoCAD", Cadence, vol. 1, No. 2, pp. 51-55.
Angell, Richard "End-to-End Design", PC Tech Journal, vol. 4, No. 11, Nov. 1986, pp. 97-119.
Clark, R. J. and Nakagawa, T., "The STD Process-New Developments and Applications", Abstract from the 1974 Microelectronics Symposium held Oct. 1974, pp. 131-144.
High Technology, Oct. 1986, p. 55.
"Embedding ICs in Plastic Cuts Interconnect Space", Electronics, Jun. 9, 1986, pp. 17 and 20.
Hennpenheimer, T. A., "Monster Chips", Popular Science, pp. 104, 106, 108 and 110.
IBM Technical Disclosure Bulletin, vol. 28, No. 5, Oct. 1985, "Lift-Off Stencil Created by Laser Ablation", p. 2034.
Egitto, F. D. et al., "Plasma Etching of Organic Materials. I. Polyimides in O.sub.2 -CF.sub.4 ", Journal of Vacuum Science & Technology/B3, (1985), May-Jun., No. 3, pp. 893-904.
Auletta, L. V. et al., "Flexible Tape Conductor Interconnection for Chips", IBM Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 1214-1215.
Lukaszek, W. et al., "CMOS Test Chip Design for Process Problem Debugging and Yield Prediction Experiments", Solid State Technology, Mar. 1986, pp. 87-93.
Auletta, L. V. et al., "Flexible Tape Conductor Interconnection for Chips", IBM Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 1214-1215.
Eichelberger Charles W.
Welles II Kenneth B.
Wojnarowski Robert J.
Davis Jr. James C.
General Electric Company
Macon Robert S.
Snyder Marvin
Whitehead A.
LandOfFree
Integrated circuit packaging configuration for rapid customized does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit packaging configuration for rapid customized , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit packaging configuration for rapid customized will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-920946