Integrated circuit packaging configuration for rapid customized

Details Integrated circuit packaging configuration for rapid customized Integrated circuit packaging configuration for rapid customized

1991-10-28

1993-05-25

Baker, Stephen M.

Excavating

371 223, G01R 3128

Patent

active

052146553

ABSTRACT:
A packaged electronics system, having respective portions each with respective input and output ports, and having interconnection busses between certain of these ports, is tested as follows. Each input port has a set of first transmission gates associated therewith for selectively disconnecting it during testing from the end of each interconnection bus connected bit during normal operation. Each input port has a second set of transmission gates associated therewith for selectively applying test vectors thereto during testing as provided in parallel form from a serially loaded shift register. Each output port connects to the input connections of a respective set of tristate drivers for selectively applying its output signals at relatively low source impedance to at least one interconnection bus connected from the output connections of that set of tristate drivers. A shift register converts the signals appearing in parallel at least one end of each interconnection bus to a concatenation of test results in serial form.

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