Integrated circuit packaging

Details Integrated circuit packaging Integrated circuit packaging

2006-04-05

2009-10-13

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S676000

Reexamination Certificate

active

07602050

ABSTRACT:
The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.

REFERENCES:
patent: 6025640 (2000-02-01), Yagi et al.
patent: 6111311 (2000-08-01), Suzuki
patent: 0272188 (1988-06-01), None
patent: 426926 (2001-03-01), None
patent: 485586 (2002-05-01), None
patent: 517374 (2003-01-01), None
International Search Report-PCT/US06/027462, International Search Authority-European Patent Office-Dec. 19, 2006.
Written Opinion-PCT/US06/027462, International Search Authority-European Patent Office-Dec. 19, 2006.

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