Integrated circuit package with optimized mold shape

Details Integrated circuit package with optimized mold shape Integrated circuit package with optimized mold shape

2007-06-19

2007-06-19

Owens, Douglas W. (Department: 2821)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S738000, C257S787000

Reexamination Certificate

active

10856705

ABSTRACT:
The invention relates to an integrated circuit package, in particular an integrated chip size package or an integrated chip scale package, comprising a substrate carrying a die, and connection elements, interconnection elements, connecting pins of said die with said connection elements, and a mold encapsulating said die on said substrate. To increase reliability and to reduce failure due to deformation stress, the invention provides said mold with reduced stiffness at areas located substantially at one of said interconnection elements providing increased flexibility of said package at said areas compared to other areas of said package.

REFERENCES:
patent: 5490324 (1996-02-01), Newman
patent: 5905633 (1999-05-01), Shim et al.
patent: 5953589 (1999-09-01), Shim et al.
patent: 6124637 (2000-09-01), Freyman et al.
patent: 6258626 (2001-07-01), Wang et al.
patent: 6291892 (2001-09-01), Yamaguchi
patent: 6779783 (2004-08-01), Kung et al.
patent: 2002/0182841 (2002-12-01), DiStefano et al.
patent: 2003/0034568 (2003-02-01), Chai et al.

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