Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2001-11-02
2004-03-23
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S666000
Reexamination Certificate
active
06710432
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit (IC) packages and methods for fabricating them. More specifically, the present invention comprises an IC package with a very low inductance ground path to a printed circuit board ground plane, wherein the same structure that provides the low inductance ground path also provides a significantly improved thermal conduction path.
BACKGROUND OF THE INVENTION
A known integrated circuit (IC) package, with an exposed die attach pad (DAP), is shown in FIG.
1
. IC package
10
consists of IC die
12
mounted on die attach pad
16
by means of a attach epoxy
14
. IC die
12
is coupled to the input/output pins of metal lead frame
18
by means of a plurality of bond wires
20
. A molded IC body
22
is then formed around IC die
12
an lead frame
18
in a known manner to complete the package. As shown in
FIG. 1
, lower surface
15
of die attach pad
16
remains exposed and co-planar with the leads of lead frame
18
after IC package
10
is completed.
Although IC package
10
is adequate for many purposes, as the operating frequencies of packaged IC dies have increased, several shortcomings of this type of package have emerged. In ICs that contain a large number of fast input/output (I/O) cells, many of the I/O cells can switch states at the same time, or nearly at the same time. This event is referred to as the “simultaneously switching output” (SSO) condition.
SSO conditions can cause very high ground bounce to occur on a (shared) on-die ground line which connects multiple I/O cells to the same (shared) on-die ground pad, which is then connected to a (shared) IC package ground pin. Ideally, the voltage on a shared on-die ground line should remain at zero volts when the I/O cells connected to this line switch from the logic high state to the logic low state. However, the bond wires and the lead frame that couple the on-die ground line to an external PCB ground plane present a collective I/O pin inductance. Rising/falling I/O cell currents, which must flow through this inductance, can cause the voltage on the on-die ground line to temporarily rise and/or fall above/below zero volts. These momentary voltage changes are often referred to as “ground bounce.” In the worst case, high ground bounce can cause an IC to malfunction. For example, in ICs which contain analog circuitry, high ground bounce can cause the analog circuitry to generate degraded and/or erroneous waveforms. Furthermore, high ground bounce can also cause digital I/O cells, which are trying to output a logic low level, to temporarily output a logic high level. This temporary “glitch” condition can easily cause system malfunction.
Ground bounce depends upon a number of factors, including the total inductance from an on-die ground pad to the PCB ground plane. This total inductance includes all wire inductance plus the inductance of the package lead frame. Ground bounce can be minimized by minimizing the total inductance from an on-die ground pad to the PCB ground plane. If the total inductance could be reduced to zero, then ground bounce would also be reduced to zero.
As shown in
FIGS. 2
a
and
2
b
, another known type of IC package, a plastic ball grid array (PBGA) offers a very direct connection to the ground plane of a PCB. PBGA IC package
30
has an IC die
32
mounted on a substrate
38
using a silver epoxy or other suitable attachment means. Substrate
38
is coupled to IC die
32
by means of bond wires
31
. Those portions of substrate
38
that have been connected to IC die
32
serve as the I/O pins of completed IC package
30
. The ground pads
40
on IC die
32
are coupled to the portion of substrate
38
that directly underlies IC die
32
by means of bond wires
36
. Solder balls
39
are formed on the lower, exposed surfaces of substrate
38
. When placed on a printed circuit board (PCB) and then heated in one of several known ways, solder balls
39
provide electrical connections with substrate
38
. Solder balls
39
which directly underlie IC die
32
provide a direct pathway from the ground pads
40
of IC die
32
through substrate
38
and solder balls
39
into the PCB ground plane. This ground path offers very low inductance to the PCB ground plane and greatly reduces ground bounce.
The two different packages shown in
FIGS. 1
,
2
a
and
2
b
each solve different problems. The exposed die attach pad of the package shown in
FIG. 1
offers significant heat sinking, which becomes increasingly important as IC operating speeds continue to increase. Indeed, the heat sinking capabilities of this type of package have been increased in some known packages by extending the die attach pad so that it protrudes outside of the package body. However, according to prior art, these protruding die attach pads are as yet restricted to protruding no further than the top surface of the PCB upon which they are mounted.
The package illustrated in
FIGS. 2
a
and
2
b
provides a very low inductance ground pathway, which greatly reduces ground bounce while simultaneously reducing the number of leads required for ground connections.
An IC package which combines the advantages of the described prior art packages, without increasing the package manufacturing cost, would be a useful advance on known IC packages.
SUMMARY OF THE INVENTION
In each of its embodiments, the present invention comprises an IC package with a very low inductance ground path to a PCB ground plane, wherein the same structure that provides the low inductance ground path also provides a significantly improved thermal conduction path. A comparatively large metal die attach pad (metal slug), with protrudes outside of the IC package, is electrically connected to IC ground pads through its upper surface, and electrically connected to a PCB ground plane through its lower, exposed surface. This connection provides a very low inductance ground path from the IC die to the PCB ground plane, while also providing a highly efficient heat sink for the IC die. In several embodiments, the metal slug is made sufficiently thick so that it extends well outside of the IC package. In these embodiments, the metal slug is inserted into pre-defined and pre-cut holes in the PCB. When attaching the IC package to the PCB, these embodiments offer the additional advantage of self-alignment of the IC package pins with their corresponding PCB traces. To further improve the present invention's thermal conduction, in those embodiments where the metal slug extends through the PCB, a heat sink can also be attached to the exposed metal slug after insertion into the PCB.
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patent: 5877552 (1999-03-01), Chiang
patent: 5892274 (1999-04-01), Buschbom
patent: 5939781 (1999-08-01), Lacap
patent: 6034423 (2000-03-01), Mostafazadeh et al.
patent: 6093960 (2000-07-01), Tao et al.
patent: 6166430 (2000-12-01), Yamaguchi
patent: 6208023 (2001-03-01), Nakayama et al.
patent: 6420779 (2002-07-01), Sharma et al.
patent: 6437427 (2002-08-01), Choi
patent: 2002/0017706 (2002-02-01), Sone
patent: 2002/0027297 (2002-03-01), Ikenaga et al.
Product Description: ASAT® “Exposed Die Pad Package” (EPP), 1 Page, Mar. 25, 1998.
Product Description: PSOP 2 and PSOP 3.
Beyer Weaver & Thomas LLP
National Semiconductor Corporation
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