Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-08-18
2002-11-05
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S691000, C257S784000, C257S786000
Reexamination Certificate
active
06476472
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits generally, and more specifically to structures and method for protecting integrated circuits against electrostatic discharge (ESD).
DESCRIPTION OF THE RELATED ART
Ball Grid Array (BGA) packages are well known. An exemplary BGA package is described in U.S. Pat. No. 5,216,278 to Lin et al., which is incorporated by reference herein in its entirety. In a BGA package, an integrated circuit (IC) die or chip is mounted on a top surface of a substrate. The substrate has a plurality of conductive traces. The IC chip has a plurality of bond pads. The bond pads of the IC chip are connected (for example, by wire bonding, tape automated bonding, or flip-chip bonding) to respective ones of the conductive traces on the top surface of the substrate. The substrate has an array of solder balls (typically in a rectangular grid) on the bottom surface opposite the surface to which the IC is mounted. The substrate has electrical paths connecting the conductive traces on the top surface to respective solder balls on the bottom surface. The package is placed on a printed wiring board, and heated to reflow the solder balls on the bottom of the substrate, to form the connections between the IC bond pads and elements on the printed wiring board. The BGA package allows a high density of connections to the printed wiring board.
To reduce manufacturing costs, it is desirable to use a single common type of substrate to accommodate different variations of an IC chip, or a family of similar chips. For this purpose, a substrate is provided with a set of conductive traces corresponding to any of the bond pads that may be present on any of the IC chips that are to be used with the same type of substrate. In any given BGA package, the IC chip may have a number of bond pads that is less than the number of conductive traces on the substrate. The extra conductive traces on the substrate are referred to herein as “no-connect pins.” For example, a substrate having a 256 ball grid array may be used with an IC that only has between 180 and 200 I/O bond pads.
A BGA package with no-connect pins typically exhibits an electrostatic discharge (ESD) threshold that is lower than an otherwise similar BGA package without no-connect pins. For example, ESD stressing on one of the no-connect pins results in a discharge through an adjacent BGA pin.
Attempts have been made to deal with the ESD problem in BGA packages with no-connect pins. Typically, the solution has been to avoid ESD testing of the no-connect pins, thus avoiding application of a high voltage charge to a no-connect pin. This is possible, because ESD specifications currently do not require ESD testing for the noconnect pins. However, it is likely that future ESD specifications will require ESD testing of the no-connect pins.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit (IC) package including an IC. The IC has at least one ESD protection circuit that provides protection against electrostatic discharge. The IC has a plurality of bond pads that are not coupled to the ESD protection circuit. The IC is connected to a substrate. The substrate has a first plurality of conductive traces, which are connected to respective bond pads of the IC, and a second plurality of conductive traces, which are not connected to any of the plurality of bond pads of the IC. Either the substrate or the IC has a common conductive trace that is connected to the ESD protection circuit. Each of the second plurality of conductive traces is connected to the common conductive trace.
REFERENCES:
patent: 4975761 (1990-12-01), Chu
patent: 5045921 (1991-09-01), Lin et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5400220 (1995-03-01), Swamy
patent: 5420460 (1995-05-01), Massingill
patent: 5506756 (1996-04-01), Haley
patent: 5541450 (1996-07-01), Jones et al.
patent: 5715127 (1998-02-01), Yu
patent: 5869870 (1999-02-01), Lin
patent: 5969929 (1999-10-01), Kleveland et al.
patent: 6008532 (1999-12-01), Carichner
patent: 6025631 (2000-02-01), Lin
patent: 6078068 (2000-06-01), Tamura
patent: 6084777 (2000-07-01), Kalidas et al.
patent: 6246566 (2001-06-01), Glenn
patent: 06232332 (1994-08-01), None
Davison Kerry L.
Hawk, Jr. Donald E.
Smooha Yehuda
Agere Systems Inc.
Chaudhuri Olik
Duane Morris LLP
Ha Nathan W.
Koffs Steven E.
LandOfFree
Integrated circuit package with improved ESD protection for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit package with improved ESD protection for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit package with improved ESD protection for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2977752