Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-10-12
2003-04-29
Nguyen, Ha Tran (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S777000, C257S778000, C257S786000, C438S108000, C438S107000, C438S406000, C438S455000, C427S096400, C427S097100, C427S098300
Reexamination Certificate
active
06555914
ABSTRACT:
FIELD
This invention generally relates to the field of printed circuit boards and integrated circuit packages. More particularly, this invention relates to reducing parasitic capacitance in the electrically conductive vias of printed circuit boards and integrated circuit packages.
BACKGROUND
Printed circuit boards and integrated circuit package substrates, typically referred to as laminates, are commonly used in the electronic industry. The laminates are often constructed from layers of material on which circuitry has been printed, such as signal lines, power planes, and ground planes. The layers of the laminate are typically electrically connected by mechanically drilling holes through electrically conductive via lands that have been etched in the electrically conductive layers of the laminate. The via lands may be used in part to align the drilling equipment and provide a suitable surface for the drilling process. Vias or plated through holes are constructed in the holes that are drilled, by plating the holes with an electrically conductive material to selectively connect the various layers, such as ground and power planes, to other circuits in the laminate.
As such laminates become smaller and smaller with the commensurate reduction in the size of integrated circuit, problems such as unwanted parasitic capacitance tend to occur between the various elements of the laminate. This parasitic capacitance becomes especially pronounced as the speed at which the circuit is operating increases.
Like other elements of the laminate, the drilled via lands of the various layers tend to induce unwanted parasitic capacitance. Furthermore, the manufacturing process of the laminates requires precision etching of the via lands and the cut outs that must surround some of the via lands. These positional and dimensional accuracies tend to be needed to maintain the accurate alignment of the via lands on different layers, such as during the lamination of the layers. If these accuracies are not met, the manufacturing yields of the laminates may be sacrificed, and as a result the cost of manufacturing the circuit boards and packages increases.
SUMMARY
The above and other needs are met by a method of forming an electrically conductive via in a layered circuit structure, such that parasitic capacitance is reduced in the electrically conductive via. The surface layers (top and bottom) of the layered circuit structure are identified, to which electrical continuity with the electrically conductive via is desired, and the secondary layers of the layered circuit structure are also identified, to which electrical continuity with the electrically conductive via is not desired.
Via lands are formed only on the surface layers, to which electrical continuity with the electrically conductive via is desired, and not on the secondary layers, to which electrical continuity with the electrically conductive via is not desired. The via lands are formed in the first portions (through hole areas) of the surface layers, where the electrically conductive via is to pass through the surface layers. Electrically nonconductive cut outs are selectively formed in second portions of the secondary layers where the electrically conductive via is to pass through the secondary layers. The cut outs have a diameter that is smaller than that which would be required had via lands been formed for the electrically conductive via on the secondary layers.
The surface layers and the secondary layers of the layered circuit structure are laminated together. The first portions of the surface layers, where the electrically conductive via is to pass through the surface layers, are aligned with the second portions of the secondary layers, where the electrically conductive via is to pass through the secondary layers. A through hole is formed through the via lands in the first portions of the surface layers, and also through the cut outs formed in the second portions of the secondary layers.
The electrically conductive via is formed in the through hole such that the electrically conductive via passes through and makes electrical contact with the via lands of the surface layers, and passes through the cut outs of the secondary layers without making electrical contact to the secondary layers. The parasitic capacitance of the electrically conductive via is reduced by not having via lands on the secondary layers.
By not having via lands on layers of the layered circuit structure that do not require electrical connection with the associated via, the parasitic capacitance associated with the via land proximity to other metallization structures is virtually eliminated, especially for circuits functioning at higher frequencies of operation. Furthermore, etching the cut outs and subsequent alignment of the layers during lamination tends to require a less precise manufacturing process without these unneeded via lands. Thus, the efficiency and yield of the manufacturing process used to build the layered circuit structure is generally increased. The current density and distribution on these circuit layers may also be enhanced, since the diameter of a cut out that doesn't surround a via land is generally smaller than the diameter of a cut out that does surround a via land.
In various preferred embodiments, the layered circuit structure further comprises one of a printed circuit board and an integrated circuit package substrate. Preferably, multiple electrically conductive vias are formed in the layered circuit structure. The cut outs are preferably formed by etching the electrically nonconductive cut outs into an electrically conductive layer on the secondary layers. The via is preferably formed by plating the through hole with copper. In a most preferred embodiment, the steps of the method are performed sequentially.
According to another aspect of the invention there is described a layered circuit structure having an electrically conductive through hole formed according to the method described above.
As previously discussed, the reduced parasitic capacitance that results from the removal of the via lands from the layered circuit structure tends to increase the performance of the layered circuit structure. In addition, the cut outs are much simpler to manufacture and align without the via lands.
REFERENCES:
patent: 5929510 (1999-07-01), Geller et al.
patent: 6016084 (2000-01-01), Sugimoto
Lim Hong T.
Patel Pradip D.
Thavarajah Manickam
Thurairajaratnam Aritharan
LSI Logic Corporation
Luedeka Neely & Graham
Nguyen Ha Tran
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