Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2003-08-07
2004-06-29
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S692000, C257S693000, C257S712000, C257S713000
Reexamination Certificate
active
06756665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the packaging of integrated circuits, and more particularly to the packaging of integrated circuits with heat-dissipating wiring.
2. Description of Related Art
During the manufacturing processes of integrated circuits, semiconductor chips arc fabricated on a wafer. Upon the manufacturing processes for semiconductor are completed, the wafer is then cut to form dies, which contain semiconductor chips. Each die is a semiconductor component, such as a dynamic-random-access memory (DRAM) module or a core logic chip. Followed by the formation of dies is the packaging process of dies, which allows semiconductor components to operate independently on package substrates. The packaging process includes preparing a package substrate, which has electrical conductive lines, such as trace lines, are provided for electrically connecting to a die. Then, the die is mounted on the package substrate, wherein the bonding wires are employed to electrically connect the semiconductor component (die) to the package substrate in the case of ordinary packaging. In addition, metal bumps are employed to electrically connect the semiconductor component (die) to the package substrate in the case of flip chip packaging. After that, the encapsulating process is performed so as to package the semiconductor component onto the package substrate.
During the manufacturing processes of integrated circuits, the designs of package substrates are determined according to the electrical and dissipating requirements of the semiconductor components.
Referring to
FIG. 1
, a schematic diagram showing a conventional package of the core logic chip mounted on a motherboard is illustrated. A core logic chip
10
is disposed on an upper surface of a substrate
11
. The core logic chip
10
connects to the signal I/O (input/output) pads of the substrate
11
via bonding wires
12
, and the signal I/O pads further connects to the ball pins
14
formed on the bottom surface of the substrate
11
via through holes
13
. However, since there are numerous power pins configured on the chip
10
, the substrate
11
is configured with a power ring
15
for connecting to the power pins via a plurality of power wires
16
. The power ring
15
further connects to the ball pins
18
formed on the bottom surface of the substrate
11
via a plurality of through holes
17
, such that an electrically connection between aforementioned elements is formed. A plastic cap
19
covering the substrate
11
is mounted on the substrate
11
and serves as a protection element of the core logic chip
10
. The core logic chip
10
is electrically connected to the signal I/O pads or the power ring
15
of the substrate
11
via the bonding wires
12
or the power wires
16
. The core logic chip
10
is then electrically connected to the ball pins
14
and
18
via metal plugs in the through hole
13
and
17
. Therefore, electrical connections to motherboard
20
are formed subsequently. By utilizing the packaging technique, the core logic chip
10
is allowed to form electrical connections to other circuit components provided on the motherboard
20
.
In the above-mentioned package structure, the power ring
15
is formed on the substrate
11
and is positioned at one side of the chip
10
. This may facilitate the wire bonding process for forming the power wires
16
to connect the chip
10
and the power ring
15
, and simplify the design of the wire arrangement. However, the power ring
15
provided on one side of the substrate
11
will sufficiently increase the thermal stress on the substrate
11
. It is because that a giant current flux flows through the power ring during the normal operation of the chip, and heat is generated. If the heat-dissipation efficiency or heat-conductive efficiency is bad, the thermal stress will occur on the substrate resulting in wrap of the substrate. In addition, the chip may become abnormal when the temperature of the substrate is too high.
Heat-dissipation efficiency has been a critical subjective in the semiconductor chips manufacturing, particularly the manufacturing of the core logic chips, which have high operating speed and integrated density. Low heat-dissipation efficiency often results in high failure frequency for integrated circuit chips. However, the drawback of employing aforementioned packaging method of the core logic chip mounted on a motherboard, wherein the core logic chip is electrically connected to the substrate via metal wires, the bottom of the core logic chip is connected to the substrate, and the substrate is connected to the motherboard with ball pads, is that such method is insufficient to satisfy higher dissipating demand required by core logic chips operation. Therefore, the subjective of the invention is to provide a solution to improve the drawback.
SUMMARY OF THE INVENTION
The invention discloses an integrated circuit package structure with heat dissipating design, wherein an integrated circuit chip is placed on a package substrate. A power ring is disposed on the substrate and around the integrated circuit chip. Parts of the power ring, neighboring the region that the integrated circuit chip would generate high heat, have larger surface areas, so as to expand the contact area between the power ring and the package substrate, and to ensure higher heat-dissipation efficiency of the integrated circuit chip.
The invention discloses the integrated circuit package structure with heat dissipating design, wherein the contact area between the power ring and the package substrate is increased, so that the package substrate conducts heat to a multi-layer circuit board via the power rings, resulting in increasing heat-dissipation efficiency of the integrated circuit chip.
The invention discloses the integrated circuit package structure with heat dissipating design, wherein the electrical connections between the substrate and a computer mother board is employed to increase the contact area of the electrical connections between the substrate and the mother board, resulting in improving the heat-dissipation efficiency.
The invention discloses the integrated circuit package structure with heat dissipating design, using a heat-dissipating metal cap provided for protecting the integrated circuit chip mounted on the package substrate, so as to increase heat-dissipation efficiency.
As mentioned above, the integrated circuit package structure of the invention has a power ring comprising a plurality of blocks, which are not connected to each other, wherein the surface area of the blocks neighboring the region that the integrated circuit chip generating more heat is larger than that of the blocks adjacent to other regions.
REFERENCES:
patent: 6424032 (2002-07-01), Ikemoto et al.
Bacon & Thomas PLLC
VIA Technologies Inc
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