Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-11-29
2001-08-28
Gaffin, Jeffrey (Department: 2841)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C361S807000, C361S809000, C361S820000, C439S488000, C439S491000, C324S757020, C257S048000
Reexamination Certificate
active
06281695
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the integrated circuit industry, and more particularly is a means of marking the pins of an integrated circuit, and further to guide a metal probe to the appropriate pin while shielding the probe from adjacent pins.
BACKGROUND OF THE INVENTION
Electronic circuit boards utilizing a multitude of integrated circuit (IC) applications are manufactured in huge numbers worldwide. Each of the IC's, or chips, includes a large number of circuits that are accessed by metal leads, or pins. Because of the increasing circuit density of the chips, a growing problem with IC's is identifying the numerous pins and their corresponding circuits.
High pin density also leads to problems when assembling, testing, and/or troubleshooting the boards. To test individual circuits, a metal probe must be brought into contact with the appropriate pin. The greater the pin density, the more difficult it is to achieve contact with the desired pin, and to avoid contact with adjacent pins. It would thus be beneficial to have a means of guiding a probe to only the desired pin.
There are several current art methods directed to the identification of the various pins on a chip. In some cases, a plastic tag is affixed to the pins of an IC in a through hole circuit board. The tag has labelled holes that receive each of the pins of the IC. This type of tag can be very difficult to use when pin density is high, due to the difficulty of aligning the tag holes with the pins. Damage to the IC can occur when attempting to mount the identifying tag. Furthermore, this type of tag can only be used on dip IC's mounted on through hole circuit boards. They cannot be used on any type of surface mount IC's.
A more thorough method of pin identification is disclosed in U.S. Pat. No. 5,051,870, “Electronic Socket Attachment Method and Identification System”, issued to John A. Companion, Sep. 24, 1991. The Companion technique envisions a matched set of adhesive labels. A first of the labels is affixed to the top surface of the chip, and a second mirror image label is affixed to lower surface. Additionally, a double-sided adhesive socket sticker is included with the identifying labels.
Clearly, the prior art methodology has technical shortcomings and/or is needlessly complex. Also, there is no convenient technique to establish a probe guide with the pin indicating means. Furthermore, this type of tag can only be used on dip IC's mounted on through hole circuit boards. They cannot be used on any type of surface mount IC's. Furthermore, there is no mechanism for guiding the label sheet so that when it is installed, misalignments between the pin labels and the IC pins do not occur.
There are several current art methods directed to the guiding of a probe to a pin on a chip. One method of this probe guide fixture is disclosed in U.S. Pat. No. 4,055,800, “Test Chip for Electronic Chips”, issued to Charles S. Fisk and Dietrich Jung, Oct. 25, 1977. This technique contains a clip like a flat top laundry cloth hanging clip. The end of the clip clamps onto the two sides of an IC. The two sides of the clip contain through holes through which one can make electrical contact with pins on the IC using long probes. Clearly, this prior art methodology has technical shortcomings and complex. First, it will not work for IC's having pins on four sides. Second, it will not be able to secure the clip onto surface mount IC's which could have a height as low as 1.5 mm and a size as large as 10 mm×10 mm.
Another method is disclosed in U.S. Pat. No. 4,460,236, “Test Apparatus for Electrical Circuit Boards”, issued to Michael G. Strautz, Jul. 17, 1984. This apparatus contains two separate components. The top component includes a flat top marking plate with metal pins starting at the top marking plate and then extending downward to make contact with the pins on an IC. The second component is a dip IC socket. The top component secures itself by means of clamping its downward wall to the side wall of the second component. Clearly, this prior art methodology has the similar technical shortcomings as mentioned previously. Its IC socket was designed for dip IC's and will not work on surface mount IC's. Also its top component does not have a mechanism for preventing a metal probe from accidentally touching two adjacent pins on the IC simultaneously. Touching two adjacent pins with a probe simultaneously during testing is disastrous and is a very important concern for an engineer or a technician. It happens very often even for a highly skillful engineer or technician. This is due to a small separation between two adjacent pins of a surface mount IC. The spacing between two adjacent pins can be less than 0.5 mm.
Accordingly, it is an object of the present invention to provide a simple, accurate means of pin identification on an IC package.
It is a further object of the present invention to provide a means of guiding a probe to a selected pin, and reducing the possibility of contact with an adjacent pin.
It is a still further object of the present invention to provide an identification method that is easily affixed to an IC package.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit package pin indicator that may include probe guides. The indicator includes a top marking plate with indicia for each of the multiple pins of the IC package. The top plate will have numerical or alpha labels for some or all of the pins, depending on the number of pins present. The top marking plate may include a securing means to attach the top marking plate to the top of the IC package and to hold the top marking plate in place. Each pin marker corresponds to a hole or slot that is adapted to guide a probe to a selected pin. The pin indicator can be used with both through hole and surface mount IC boards.
An advantage of the present invention is that the indicator is accurate, and is easily installed on the IC package.
Another advantage of the present invention is that an integral probe guide is provided for a tester or debug operation.
These and other objects and advantages of the present invention will become apparent to those skilled in the art in view of the description of the best presently known mode of carrying out the invention as described herein and as illustrated in the drawings.
REFERENCES:
patent: 3551878 (1970-12-01), Rossman
patent: 4055800 (1977-10-01), Fisk et al.
patent: 4305767 (1981-12-01), Corey
patent: 4340774 (1982-07-01), Nilsson et al.
patent: 4460236 (1984-07-01), Strautz
patent: 5051870 (1991-09-01), Companion
patent: 5525812 (1996-06-01), Bandzuch et al.
patent: 5557504 (1996-09-01), Siegel et al.
patent: 5883788 (1999-03-01), Ondricek et al.
patent: 5909122 (1999-06-01), Chung et al.
Chung Elynna M. C.
Chung Robbie M. K.
Gaffin Jeffrey
The Kline Law Firm
Vigushin John B.
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