Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-08-30
2002-09-10
Talbott, David L. (Department: 2827)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S767000, C361S783000, C257S209000, C257S529000, C257S700000, C257S922000, C257S530000, C438S132000, C438S131000
Reexamination Certificate
active
06449170
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits, and more particularly, to the prevention of tampering with the operating parameters for integrated circuitry.
DESCRIPTION OF THE RELATED ART
Integrated circuits such as microprocessors can be run at different clock speeds and with different supply voltages. The determination of what is the appropriate clock speed and appropriate voltage depends on many factors. A higher clock speed requires a higher supply voltage. In addition, the higher clock speed results in additional heat and power being dissipated. Microprocessors utilized in mobile applications are particularly sensitive to power dissipation and generally require the lowest power dissipation and thus require the lowest supply voltage that can achieve the rated clock speed. Microprocessors used in desktop applications are less sensitive to power dissipation considerations.
In general, microprocessor product yield, performance (MHz) and reliability are affected by the voltage supply setting. Within a range of only several hundred millivolts, dramatic differences can be seen in yield, performance and reliability, even from the same wafer lot. Choosing the best voltage is usually a compromise of yield, performance and reliability since the same value of voltage is usually chosen for a large population.
A higher percentage of a given population of microprocessors could operate at higher performance levels (thus creating higher revenue) if each microprocessor could operate at its own specific voltage. One solution would be to mark each processor with a number or symbol indicating its voltage and/or speed rating. However, that provides no guarantee that the appropriate voltage is supplied to the microprocessor in the final system.
Referring to
FIG. 1
, one prior art approach for providing the appropriate voltage and frequency values in a computer system is illustrated. Central processing unit (CPU)
101
receives bus frequency signals
103
(BF[2:0]), which provide a multiplier used by the processor to multiply a bus clock (not shown). The multiplied bus clock is used by the CPU to clock its internal logic. CPU
101
also receives core voltage
105
(commonly referred to in x86 architectures as Vcc2) from CPU core voltage regulator
107
. Other voltages, which are typically supplied to the CPU, e.g., Vcc3 (I/
0
voltage) are not shown. Core voltage regulator
107
is programmable and receives voltage control inputs
109
(also referred to as voltage ID (VID) signals) which determine the voltage level supplied to CPU
101
. The values for the both the VID signals and the BF pins are provided by the settings ofjumpers
111
.
It is important that a microprocessor is not run at clock speeds in excess of the speed determined by the manufacturer's testing procedure and guaranteed by the manufacturer. Operating he microprocessor above the manufacturer's specifications creates potential reliability issues that can cause the microprocessor and/or end user applications to malfunction and to fail.
It is conceivable to set the jumpers to correspond to the marking (number or symbol) on the processor that indicates its voltage and/or speed rating. However, that approach provides no guarantee that appropriate voltage and frequency settings will be utilized. In fact, certain unscrupulous suppliers of computer systems have been known to provide systems having higher than recommended voltages and frequencies. Since companies typically qualify and validate chips at certain voltage and frequencies, such over clocking or excessive voltage can result in shorter product lifetimes, decreased reliability and excessive product returns.
Further, systems with an overclocked microprocessor can be sold at a premium which is unjustified. Failure of such systems to operate properly at the mismarked speed cause end user dissatisfaction with the system. This end user dissatisfaction is usually directed at the manufacturer and results in damage to the manufacturer's reputation, goodwill, and can affect future sales. The sale of such overclocked systems can cost microprocessor chip manufacturers millions of dollars in lost sales (of properly marked higher speed microprocessors as well as future sales) and in repair and replacement costs. In addition, manufacturers have sometimes been put in the position of having to replace mismarked parts to protect their reputation.
Thus, it would be desirable to minimize the opportunity for deliberate overclocking or over voltage. Further, it would be desirable to obtain higher aggregate performance from a given population of microprocessors without unduly complicating the manufacturing process.
SUMMARY OF THE INVENTION
There is a need for a programmable semiconductor device package arrangement and method of programming the same in which the opportunity for deliberate overclocking or over voltage is minimized.
There is also a need for a programmable semiconductor device package arrangement and method of programming the same in which programming elements are positioned on a package substrate so as to obfuscate the programming elements from an unscrupulous supplier.
This and other needs are met by embodiments of the present invention which provide a package for mounting at least one integrated circuit die comprising a package substrate that includes a bottom surface having first connectors configured for electrically connecting the package to a circuit board. The top surface opposite the bottom surface of the package substrate has second connectors configured for electrically connecting a semiconductor device to the package. One-time programmable elements are provided on a surface other than the top surface and have a first and a second end separated by a programmable link. The first end of the one-time programmable element is coupled to a power supply voltage node in the package. These one-time programmable elements are programmable to adapt the package to different semiconductor devices having different operating parameters. Embodiments of the invention include providing the one-time programmable elements on a side surface or a bottom surface of the package.
By the provision of programmable elements on a side surface or a bottom surface of the package, rather than the top surface, the possibility that the programmable elements will be located and reworked is reduced. Shorter product lifetimes, decreased reliability, consumer dissatisfaction, and excessive product returns that otherwise may result are minimized.
The earlier-stated needs are also met by another embodiment of the present invention which provides a method of configuring a circuit board and package arrangement comprising the steps of electrically and mechanically connecting an integrated circuit to a top surface of a package board. The integrated circuit is configured to operate within specified operating parameters. Programmable elements positioned on at least one surface of the package board other than the top surface of the package board are programmed to adapt the package board to the specified operating parameters of the integrated circuit.
REFERENCES:
patent: 4706165 (1987-11-01), Takenaka et al.
patent: 5039628 (1991-08-01), Carey
patent: 5288949 (1994-02-01), Crafts
patent: 5953216 (1999-09-01), Farnworth et al.
patent: 6026221 (2000-02-01), Ellison et al.
patent: 6191482 (2001-02-01), Senba et al.
Anderson Charles
Casto James J.
Nguyen Quang D.
Tain Alexander C.
Talbott David L.
Vigushin John B.
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