Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
1998-12-11
2001-04-03
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S723000, C257S696000, C257S693000, C257S692000, C257S698000, C257S666000, C257S712000, C257S675000, C257S713000, C361S719000, C174S050510
Reexamination Certificate
active
06211564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to integrated circuits (IC) having external terminals. More particularly, the present invention is directed to IC packages that hold an integrated circuit (i.e., electronic circuit chip) therein that is electrically connected to terminals of the IC package that extend outside of the package, and are thus termed external terminals, which are formed in plural steps. The plural steps of external terminals reduces the required area (i.e., footprint) required to support the IC package on a circuit board.
2. Discussion of the Related Art
One type of IC package is described in Japanese Unexamined Patent Publication (KOKAI) No. 6-61363. This IC package attempts to prevent the external terminals of the IC package from being transformed in shape during ordinary use, by locating the wide portions of the external terminals in a hounds-tooth configuration so as to keep limited clearance between the respective terminals.
Electric circuit chips may be reduced in area by way of improvements in semiconductor manufacturing processes. However, simply by reducing the size of the chip does not solve a problem regarding how to package the chip in a configuration that provides terminals that may be easily electrically and physically connected to circuit boards. A limitation with the package itself regards the lead pitch (i.e., the relative spacing between external terminals) in order to meet manufacturing tolerances, physical restrictions on board use, and electrical considerations regarding isolation between the terminals. Thus, even if further reductions in chip size are possible, when the chips are placed within the package the overall package size is not necessarily reduced because the pitch of the external pins for the package limits the overall footprint of the device.
Some packages such as Quad Flat Package (QFP) have a feature that allows pin pitch to be 0.4 mm, as a limit generally. Accordingly, in these configurations, even though the chip size is reduced, the overall package size once again is limited by the pin pitch, commonly restricted to 0.4 mm. In products that require a large number of external pins, there is the distinct possibility that the size of the package will be 10 times as large as the chip itself (when comparing the respective footprints of the chip and the package).
FIG. 2
is an example of a conventional package and chip, which is viewed from a top view. A pitch of the external terminals in this case is required to be more than 0.4 mm and as a general rule for manufacturing and reliability purposes cannot be less than 0.4 mm. Accordingly, the size of this package
12
, as shown in
FIG. 2
, is larger than the internal chip
10
, and the distance between the package
12
and the chip
10
results in a significant amount of useless space around the chip that takes up perhaps valuable real estate on a circuit board. Conventional approaches have not adequately addressed this problem, as determined by the present inventor.
Moreover, using conventional techniques, it has not been possible for the overall IC package to be reduced in size due to a requirement of maintaining a minimum lead pitch. However, with more complex chips that require additional external pins, the overall package size of products has been increasing, yet the amount of real estate allocated for more modern IC components is being reduced as modern electronic are generally shrinking in size.
SUMMARY OF THE INVENTION
An object of the present invention is to address the above-mentioned and other problems associated with integrated circuits having a plurality of external terminals.
A characteristic feature of the present invention is an IC package with external terminals having plural “steps” arranged in a multi-layered architecture. Using the multilayer arrangement of external terminals, it is possible to solve the conventional problem and reduce the overall package size so as to maintain a significant efficiency between the difference in chip area and IC package area. By implementing the stepped feature of the present invention it is possible to raise the efficiency of the chip itself in the package, by efficient connection of the terminal so as to reduce heat and noise in the package itself and reduce the overall thickness of the package, relative to a modular type IC package that holds multiple chips therein.
Accordingly, a feature of the present invention is an IC package having external terminals arranged in sets of plural steps, having a common pitch. Another feature is an IC package that holds more than one electric circuit chips therein and having external terminals arranged in plural steps, where the external terminals connect to the respective electric circuit chips inside of the IC package. A further feature of the present invention is the inclusion of a radiation plate that helps suppress noise within the IC package and being connected with a portion of the external terminals, that portion not being connected to the electric circuit chips inside of the IC package. These external terminals may be connected to the chips and plate by way of wire bonding, or use of an electric adhesive.
Advantages of the present invention, and particularly using the arrangement of plural steps for the external terminals is that the overall package size and total volume of the IC package is reduced. An efficient use of the external terminals is an advantage of connecting the external terminals to more than one chip within the IC package. Using the plate offers the possibility of reducing electric noise, which if not suppressed gives rise to electric signal disturbances. A second advantage of using a plate is that is able to radiate heat from the package, where the heat itself is generated by the chips within the IC package. Wire bonding for connecting the external terminals to the chips makes it possible to efficiently conduct electric signals and heat through wires in a convenient, manufacturable way. With regard to the electric adhesive, the electric adhesives allow for thickness reduction of the overall package, thereby giving rise to the possibility of including more chips within the IC package.
REFERENCES:
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5386343 (1995-01-01), Pao
patent: 5754408 (1998-05-01), Derouiche
patent: 5790378 (1998-08-01), Chillara
patent: 5824950 (1998-10-01), Mosley et al.
patent: 5844177 (1999-01-01), Sundstrom
patent: 5910685 (1999-06-01), Watanabe et al.
patent: 6005778 (1999-12-01), Spielberger et al.
patent: 6051886 (2000-04-01), Fogal et al.
patent: 6-61363 (1994-03-01), None
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Ricoh & Company, Ltd.
Williams Alexander O.
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