Integrated circuit package having signal traces interposed betwe

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

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257778, 257690, 257693, H01L 2352, H01L 2348, H01L 2940

Patent

active

060085347

ABSTRACT:
A semiconductor device package is presented having signal traces interposed between power and ground conductors in order to form stripline transmission lines. The semiconductor device package includes a substrate having a die area defined upon an upper surface. The die area is dimensioned to receive the integrated circuit. A first planar conductive layer formed upon the upper surface includes a first set of bonding pads and a set of conductive traces. Members of the first set of bonding pads are arranged upon the upper surface proximate the die area, and are used to make electrical connections to the integrated circuit. Members of the set of conductive traces are connected between one of two polarities of a power supply and corresponding members of the first set of bonding pads, and function as reference planes for underlying signal traces. A second planar conductive layer is positioned between the first planar conductive layer and an underside surface of the substrate. The second conductive layer is connected to the other of the two polarities of the power supply, and also functions as a reference plane for signal traces within the substrate. A planar conductive signal layer is interposed between the first and second conductive layers and patterned to form a set of signal traces. The signal traces form stripline transmission lines which are highly desirable in high frequency applications as their impedances are highly predictable and controllable.

REFERENCES:
patent: 5708296 (1998-01-01), Bhansali
patent: 5714801 (1998-02-01), Yano et al.
patent: 5763947 (1998-06-01), Bartley
patent: 5847936 (1998-12-01), Forehand et al.
patent: 5898217 (1999-04-01), Johnston

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