Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2007-11-28
2010-12-28
Nguyen, Ha Tran T (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
07858402
ABSTRACT:
Methods, systems, and apparatuses are provided for integrated circuit packages and for enabling electrostatic discharge (ESD) testing of the same. A package includes an integrated circuit chip, a substrate, a first electrically conductive trace, and a second electrically conductive trace. The substrate includes a first electrically conductive region and a second electrically conductive region. The first region is coupled to a first ground signal of the chip, and the second region is coupled to a second ground signal of the chip. The first trace is coupled to the first region and the second trace is coupled to the second region. A portion of the first trace is proximate to a portion of the second trace. An electrically conductive material may be deposited to electrically couple the first and second traces to enable ESD protection testing of the package.
REFERENCES:
patent: 2004/0108577 (2004-06-01), Okamoto
patent: 2004/0183167 (2004-09-01), Hortaleza et al.
patent: 2007/0235849 (2007-10-01), Othieno et al.
patent: 2007/0251720 (2007-11-01), Wright
patent: 2009/0066354 (2009-03-01), Gaertner et al.
Broadcom Corporation
Campbell Shaun
Fiala & Weaver P.L.L.C.
Nguyen Ha Tran T
LandOfFree
Integrated circuit package having reversible ESD protection does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit package having reversible ESD protection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit package having reversible ESD protection will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4161269