Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-07-21
2002-10-15
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S697000
Reexamination Certificate
active
06465882
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, more particularly, to packages for integrated circuits and methods for manufacturing those packages.
BACKGROUND OF THE INVENTION
Ball grid array (BGA) integrated circuit packages (hereinafter BGA packages) are widely used for mounting integrated circuit chips because they provide several advantages over other packaging technologies. BGA packages allow multiple pin structures to be mounted in limited surface areas. Further, BGA packages are less susceptible to impact damage because the outer terminals of the BGA package are short and stubby. In addition, the BGA package has relatively short bond pad to solder ball traces that result in improved electrical performance.
FIG. 8
illustrates a typical BGA package. The BGA package includes a substrate
1
, which may consist of a double sided or multi-layer structure, an integrated circuit chip
3
mounted on the upper surface of the substrate
1
by an adhesive
2
. Metal wires
4
electrically interconnect a plurality of bond pads
3
a
formed on the upper surface of the integrated circuit with bond pads
7
formed on the substrate
1
. Also provided is a molding section
5
formed on the upper surface of the substrate
1
to encapsulate the integrated circuit chip
3
and the metal wires
4
. Solder balls
6
are attached on the lower surface of the substrate
1
. The bond pads
7
are connected to the solder balls
6
using plated through holes
8
formed in the substrate
1
.
To fabricate this BGA package, the integrated circuit chip
3
is attached to the upper central portion of the substrate
1
by an adhesive
2
in a die bonding process. Thereafter, in a wire bonding process, the bond pads
3
a
formed on the upper surface of the integrated circuit
3
and the bond pads
7
formed on the substrate
1
are interconnected with the metal wires
4
. Using a molding process, the integrated circuit
3
, the metal wires
4
, and a portion of the upper surface of the substrate
1
are encapsulated with epoxy to form the molding section
5
. In a solder ball attaching process, the solder balls
6
are attached to the lower surface of the substrate
1
.
While this BGA package provides advantages it does, however, have its drawbacks. For example, a large number of through holes are formed in the substrate
1
, of a multi-layer metallization structure, between the power and ground rings, and the respective internal planes. As a result, the electrical performance is degraded because the conductive paths for current flow through the internal power and ground planes are reduced. Accordingly, it is desirable to develop a BGA package that reduces this problem.
SUMMARY OF THE INVENTION
The present invention is directed to an integrated circuit package such as a BGA package for use with an integrated circuit chip. The substrate of the integrated circuit package has a cavity that exposes a lower conductive level in the substrate so that connections between the integrated circuit and the lower conductive level may be formed; thus reducing the need for plated through hole connections from conductive layer to conductive layer. As a result, the conductive paths in the internal power and ground planes are not necessarily cut off by the plated through holes thus avoiding or reducing some of the electrical performance degradation suffered by prior techniques. In addition, the invention allows more signals to be added and/or the size of the integrated circuit to be reduced for enhanced electrical performance. The multiple bonding tier integrated circuit package may also provide greater wire separation that eases wire bonding and subsequent encapsulation processes.
Illustratively, the substrate of the integrated circuit package includes a conductive layer formed above a first dielectric layer and a second dielectric layer formed above the first conductive layer. The second dielectric layer has a cavity exposing a portion of the first conductive layer. Also provided is an integrated circuit, positioned above the second dielectric layer, coupled to the exposed portion of the first conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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patent: 5640048 (1997-06-01), Selna
patent: 5689091 (1997-11-01), Hamzehdoost et al.
patent: 6137168 (2000-10-01), Kirkman
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patent: WO 96/23612 (1996-08-01), None
Cohn Charles
Hawk, Jr. Donald Earl
Agere Systems Guardian Corp.
Cao Phat X.
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