Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-11-28
2002-10-15
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S706000, C257S710000, C257S712000
Reexamination Certificate
active
06465890
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit packages. More specifically, the present invention relates to integrated circuit packages having multi-layered laminated substrates including conductive layers that are segmented by split lines.
BACKGROUND OF THE INVENTION
Current advances in the design of integrated circuit dice have resulted in dice having increased circuit density, functionality, and speed. To effectively utilize these advances, integrated circuit packaging has developed to provide greater external contact density for the die and to reduce noise generated from the high density of electrical paths in the package.
One type of integrated circuit package that is frequently used in packaging the high performance dice is a grid array-type package, such as pin grid array and ball grid array packages. In some implementations, a multi-layer laminate substrate is used to support the die. The substrate is generally formed of electrically conductive layers, such as copper foil, interleaved with electrically insulating layers, such as prepreg layers formed of bizmaleimide trazine (BT) resin materials. Examples of conductive layers include signal/trace layers, power plane layers, and ground plane layers. Typically, the outermost layers of the substrate, such as the top and/or bottom surfaces of the substrate, contain the signal/trace layers and the power and/or ground layers are located between the top and bottom surfaces.
The layers are generally adhered together by an epoxy resin or an adhesive sheet, such as prepreg. Frequently, a resist is also coated on a surface of the internally located layers to flatten the surface and enhance the adhesion between the layers. Pressure and heat are then applied to the multi-layered structure to effect the lamination.
Vias are then drilled, or laser ablated, in the substrate and plated to form conductors for electrical connections between the various conductive layers. The number of electrically insulating layers, conductive layers and vias depends upon the integrated circuit die to be packaged.
Contact lands are formed on selected portions of the traces on the outermost conductive layer of the substrate. These contact lands are connected to associated bond pads of the die by conductive traces, conductive vias and bond wires. Contacts, such as solder balls, are formed on the contact lands, and allow interconnection of the package to another substrate, such as a printed circuit board.
Some high performance dice may be designed with a variety of circuits that may require different power supplies. Frequently, when more than three power supplies are used, the power plane layers of the package may be split into segments which support different power levels on the same power plane layer. Each of the segments are divided by split lines that isolate each of the different segments and prevent electrical interconnection of the segments. Typically, split lines are formed by creating areas where no conductive material is present, for example, by etching away portions of the conductive layer to form a non-conductive split line. Frequently, the ground plane layers of the substrate are also similarly split into separate segments that vertically align with the power plane segments in the substrate.
For example, mixed signal dice, include both analog and digital circuits. Often these dice are designed with all or most of the analog functionality on one side of the die with the remaining sides having the digital functionality. When designing the packages for these dice, frequently, some of the power and ground layers of the substrate are split into segments that support analog or digital circuitry.
FIG. 1
is a generalized diagrammatic illustration of a top view of a power or ground plane layer of an integrated circuit package substrate showing a division of the layer into segments supporting different power requirements. As illustrated, the layer
100
may be divided into 3 segments supporting different circuitry of the die. For example, in supporting a die having both digital and analog circuitry, the layer
100
may be a power plane layer divided into two segments supporting different digital powered circuitry and one segment supporting analog circuitry. For example, segments
102
and
104
may support digital circuitry requiring 3.3 V and 2.5 V, respectively; and segment
106
may support analog powered circuitry. The layer
100
may also be a ground plane layer similarly divided into separate segments that provide ground to the respective circuits of the die.
FIG. 2
is a diagrammatic illustration of conventionally formed split lines in the power and ground plane layers of a laminated substrate. In the illustration, the conductive layers
202
,
212
and
222
are shown in relative alignment to each other when laminated in the substrate. It will be appreciated that the layers may be power or ground plane layers that may be differently ordered and that a greater or lesser number of each of the layers may be present in some substrates. Further, as earlier described, electrically isolating layers are typically located between the conductive layers in a laminated substrate.
Conductive layer
202
may be a ground plane layer having split lines
210
which divide it into electrically isolated segments. For example, segments
204
,
206
may serve as ground to differently powered digital circuitry and segment
208
may serve as ground to analog circuitry. As earlier described, typically, the split lines
204
are formed by creating areas where no conductive material is present, and isolate each of the segments
204
,
206
, and
208
from the others.
Conductive layer
212
may be a power plane having similarly formed split lines
220
which divide it into corresponding segments which support different power requirements of the die. For example, segment
214
may conduct power of 3.3 V to digital circuitry; segment
216
may conduct power of 2.5 V to digital circuitry; and, segment
218
may serve as sub-ground to analog circuitry.
Conductive layer
222
may be also be a power plane having similarly formed split lines
230
which divide it into corresponding segments which support different power requirements of the die. For example, segment
224
may conduct power of 3.3 V to digital circuitry; segment
226
may conduct power of 2.5 V to digital circuitry; and, segment
228
may conduct power to analog circuitry.
Conventionally, the split lines
210
,
220
, and
230
are similarly formed in a substantially linear pattern and are located on each layer so that when the various layers of the substrate are stacked and laminated together, each of the split lines substantially align over one another and match in pattern.
During the lamination process, it is not possible to apply pressure uniformly across the entire substrate due to the absence of material in the split lines, and, thus, the split lines are weak links for delamination due to their substantially same patterning and direct overlaid alignment in the stacked substrate. A current problem observed in laminated package substrates having segmented layers, e.g., layers with split lines, is points of delamination corresponding to the location of the split lines. These delaminations result in defective packages and reduced yield.
Consequently, there is a need for reducing delaminations in laminated package substrates having split conductive layers.
SUMMARY OF THE INVENTION
To achieve the foregoing, and in accordance with the purpose of the present invention, there are described integrated circuit packages having offset segmentation, or splitting, of package power and/or ground layers and methods for preventing delamination in package substrates having segmented power and/or ground layers.
According to one embodiment, there is described a substrate for use in an integrated circuit package. The substrate includes a plurality of split power and/or ground plane layers that are isolated by split lines. The split lines from at least two of the split power and/or ground pla
Poddar Anindya
The Ka Heng
Beyer Weaver & Thomas LLP
Elms Richard
Menz Douglas
National Semiconductor Corporation
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