Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-11-28
2003-01-21
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S666000, C257S670000, C257S676000, C257S692000, C257S693000, C257S723000
Reexamination Certificate
active
06509635
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit packages. More specifically, the present invention relates to grid array-type integrated circuit packages.
BACKGROUND OF THE INVENTION
Current industry emphasis on decreased size and increased functionality of semiconductor dice has resulted in the continuing development of integrated circuit dice having a high density of active circuits, or cells. Conventionally, each cell has a bond pad fabricated at the surface of the die that serves as the input/output (I/O) contact for the cell. Typically, the bond pads are located along the edges of each side of the die for ease of connection of the bond pads to electrical contacts on another substrate, such as bond fingers on a package substrate. While a die may have analog and/or digital circuits, a growing number of dice, especially in networking products, include both.
Mixed signal dice have both analog and digital circuits. These dice are often rectangular in shape to accommodate the sizing requirements of the products they are installed in. Further, they are typically designed with the analog circuits isolated to one side of the die from the digital circuits. As analog cells are generally larger than digital cells, the analog side of the die tends to have a lower density of bond pads than an opposite digital side of the die. A result of this is that, when the die is packaged, the analog side of the die may require a significantly lower number of signal routings from the bond pads to the package than an opposite digital side.
Most high density integrated circuit dice are conventionally incorporated into an integrated circuit package to protect the die and provide a large number of external contacts to allow conductive interconnection of the packaged die to another substrate. One type of package that is widely used in packaging high-density dice, including those having both analog and digital circuits, is a grid array-type package. Examples of grid array-type packages include pin grid array packages, ball grid array packages, and various surface mount grid array packages.
Generally, some grid array-type packages centrally mount the die on the surface of the package substrate, for example, a plastic ball grid array package; while, some others, mount the die in a die cavity centrally formed in the substrate, for example, an enhanced ball grid array package. Currently, these packages tend to be symmetric in shape, for example, 35-mm×35-mm, 40-mm×40-mm, etc.
FIG. 1
is a diagrammatic illustration of a cross-sectional view of a conventional plastic ball grid array package having a die centrally mounted on the surface of the substrate. Package
100
includes a substrate
102
having a die
104
centrally mounted on the top surface. Bond fingers
106
, peripheral to the die
104
, are formed on the surface of the substrate
102
. The bond fingers
106
are typically connected by traces
118
to associated conductive vias
108
which pass through the substrate
102
and connect to associated contact landings
110
, on the opposite surface of the substrate
102
, on which contacts
112
, such as solder balls, are formed. Bond pads
114
of the die
104
are connected to the bond fingers
106
, for example, by wire bonding, to provide conductive interconnection of the die
104
to the contacts
112
. Typically, an encapsulant
116
, e.g., a plastic cap, is molded over the die
104
and the wires.
While the ball grid array package of
FIG. 1
is suitable for many purposes, it has a limited heat dissipation capability. For dice requiring higher heat dissipation or other package properties, other package structures have been developed. Many of these designs mount the die within a cavity in the substrate so that the die is thermally connected to a heat-dissipating layer of the substrate. The package may then be mounted on another substrate, such as a printed circuit board, so that the heat-dissipating layer is facing out.
FIG. 2
is a diagrammatic illustration of a cross-sectional view of a conventional enhanced ball grid array-type package having a die mounted in a central die cavity formed in the package substrate. Package
200
includes a substrate
202
having a die
204
located in a central die cavity
206
. Typically, the substrate
202
includes a thermally conductive layer
208
, such as a copper plate, and the cavity
206
is formed in the surface of the substrate
202
exposing a portion of the conductive layer
208
within the cavity
206
. The die
204
is mounted on the substrate
202
within the die cavity
206
and thermally connected to the conductive layer
208
of the substrate
202
. Bond pads
212
on the die
204
are electrically connected to bond fingers
210
formed on the top surface of the substrate
202
, for example, by wire bonds
214
. Conductive traces
220
routed across the surface of the substrate
202
electrically interconnect the bond fingers
210
to contact landings
216
on which contacts
218
, such as solder balls, are formed. In some package designs, the bond fingers
210
, traces
220
, and contact landings
216
may be formed on a laminate layer of the substrate
202
. A resin dam is formed on the surface of the substrate
202
to contain an encapsulant
222
formed over the die
204
and wire bonds
214
.
When packaging a die where a significantly greater number of signal routings may be required from one side of the die than from an opposite side of the die, available routing space is one determinant of the package size. If enough routing space is not available on the substrate to route signals from one side of a die, often a larger package size is required to effect the required routings.
FIG. 3
is a diagrammatic illustration of a top view of the substrate of the enhanced ball grid array-type package of FIG.
2
. For sake of clarity and ease of description, only a small exemplary portion of the bond fingers and traces are shown in the present illustration. In use, a much greater number may be present.
In
FIG. 3
, the intersection of the bisecting lines X and Y indicates substantially the center point
224
of the surface of the substrate
202
. Conventionally, the die cavity
206
is centrally formed about the center point
224
of the surface of the substrate
202
. Note that while the package substrate
202
is symmetric, the die cavity
206
is rectangular in shape to accommodate a die, such as a networking die, earlier described. Thus, substantially, D
1
=D
3
and D
2
=D
4
. The bond fingers
210
are typically located a specified distance, D
5
, peripheral to the die cavity
206
, and contact landings
216
are located in a grid array formation peripheral to the bond fingers
210
. Thus, there is a limited amount of surface area on the substrate
202
for use in routing the traces
220
between the bond fingers
210
and the contact landings
216
, e.g., the surface area described by D
1
, D
2
, D
3
, and D
4
.
For example, suppose the substrate
202
is 35-mm×35-mm having a grid array formation of contact landings
216
peripheral to the bond fingers
210
and central die cavity
206
such that D
1
=D
3
. The die to be packaged has a high density of bond pads so that it is necessary to route, for example, 22 signals from the top left of the die to contact landings
216
within a perpendicular distance
230
of 2.6921-mm. In this example, the perpendicular distance
230
may be measured as the distance between the perpendiculars drawn from the outermost bond fingers
210
, to be routed from, to contact landings
216
to be routed to. However, to accomplish this routing using 75&mgr; trace lines and space traces, the minimum distance needed is 22 signals×(75+75) &mgr;/signal=3.3-mm. Thus, a larger substrate having a greater substrate area between the bond fingers
210
and contact bond pads
208
, e.g., a greater D
1
, will be needed to achieve the 3.3-mm distance and effect the routings.
When the die is relatively uniform in its distribution of bond pa
Beyer Weaver & Thomas
Elms Richard
Menz Douglas M
National Semiconductor Corporation
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