Integrated circuit package for semiconductor devices with...

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

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C257S784000, C257S786000, C257S676000, C257S691000, C257S696000, C257S698000, C257S787000, C257S728000, C257S724000

Reexamination Certificate

active

06841852

ABSTRACT:
A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

REFERENCES:
patent: 4934820 (1990-06-01), Takahashi et al.
patent: 6184585 (2001-02-01), Martinez et al.
patent: 6373078 (2002-04-01), Yea
patent: 6448643 (2002-09-01), Cheah et al.
patent: 6593622 (2003-07-01), Kinzer et al.
patent: 20020066962 (2002-06-01), Embong et al.
patent: 20020163070 (2002-11-01), Choi
patent: 20030107120 (2003-06-01), Connah et al.

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