Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...
Reexamination Certificate
2000-04-26
2002-09-17
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Outside periphery of package having specified shape or...
C257S687000, C257S710000, C257S729000
Reexamination Certificate
active
06452268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to an integrated circuit package having an encapsulating body with a flanged portion and a molding tool for molding the encapsulating body.
2. Description of Related Art
The BGA (Ball Grind Array) integrated circuit package allows an integrated circuit package to be made very small in size while nevertheless providing highly integrated functionality from a single integrated circuit package. By the BGA technology, a substrate is used as the chip carrier for the mounting of at least one integrated circuit chip thereon, and an encapsulating body is then formed to encapsulate the integrated circuit chip. The encapsulating body is typically formed through the use of an encapsulating mold including an upper mold and an opposing lower mold.
FIG. 6
is a schematic sectional diagram used to depict the fabrication of an encapsulating body for a BGA integrated circuit package. As shown, the BGA integrated circuit package includes an integrated circuit chip
10
mounted on a substrate
11
. During the molding process, the semi-finished package configuration of the integrated circuit chip
10
and the substrate
11
is clamped between an upper mold
12
and a lower mold
13
. The upper mold
12
is formed with an encapsulating-body cavity
14
. When the upper mold
12
and the lower mold
13
are combined, an encapsulating material such as epoxy resin is filled into the encapsulating-body cavity
14
to thereby form an encapsulating body
15
therein.
In the foregoing integrated circuit package configuration, since the substrate
11
would have a thickness deviation of ±0.05 mm due to imprecision in fabrication, it would lead to the following problems during the molding process when the upper mold
12
and the lower mold
13
are combined to clamp the substrate
11
.
First, when the substrate
11
is being clamped forcibly by the two mold halves, the thicker part thereof would be unduly pressed, thus resulting in the undesired forming of micro-cracks in the solder mask coated over the substrate
11
, which would adversely affect the reliability of the internal circuitry of the resulted integrated circuit package.
Second, if the clamping force is reduced to prevent the above-mentioned problem, it would nevertheless allow a gap to be left between the bottom surface of the upper mold
12
and the top surface of the thinner part of the substrate
11
, which would allow the flowing resin used in the molding process to flow through this cap, thus undesirably resulting in the flash of the resin over the top surface of the substrate
11
. Although the flash can be later cleaned away, it would increase the overall manufacture cost and degrade the quality of the manufactured package.
Third, although the clamping force can be adjusted by a floating mechanism installed on the molds, it would be difficult to adjust for a suitable clamping force that would solve both of the above-mentioned two problems.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide an improved integrated circuit package, which can help prevent the flash of resin during the molding process for the encapsulating body.
It is another objective of this invention to provide an improved integrated circuit package, which can help prevent the forming of micro-cracks on as well as the flash of resin over the substrate during the molding process.
It is still another objective of this invention to provide an improved integrated circuit package, which can be manufactured without requiring a post-treatment process to clean away flash so as to allow the overall manufacture process more cost-effective to carry out.
In accordance with the forgoing and other objectives, the invention proposes an improved integrated circuit package which can help eliminate the above-mentioned problems of the prior art.
The integrated circuit package of the invention includes a substrate; an integrated circuit chip mounted on the substrate and electrically coupled to the substrate; and an encapsulating body for encapsulating the integrated circuit chip and part of the substrate, which is formed with an outwardly-extending flanged portion on the rim thereof at the junction between the encapsulating body and the substrate.
In accordance with the invention, the encapsulating mold used to form the encapsulating body includes an upper mold having an encapsulating-body cavity in communication with a constricted cutaway portion formed on the rim of the encapsulating-body cavity; and a lower mold for combination with the upper mold during molding process for the molding of the encapsulating body.
During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would be less likely to flash onto the surface parts of the substrate beyond the encapsulating body. This benefit allows the clamping force from the two mold halves to be reduced to a lower level that would hardly cause the forming of micro-cracks in the substrate as in the case of the prior art where a larger clamping force is required. The invention is therefore more advantageous to use than the prior art.
REFERENCES:
patent: 4768081 (1988-08-01), Moeller
patent: 5436407 (1995-07-01), Fehr et al.
patent: 5859475 (1999-01-01), Freyman et al.
patent: 6072239 (2000-06-01), Yoneda et al.
patent: 6075289 (2000-06-01), Distefano
patent: 6144107 (2000-11-01), Narita
patent: 6177724 (2001-01-01), Sawai
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Ngo Ngan V.
Siliconware Precision Industries Co. Ltd.
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