Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-12-19
2002-12-03
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S691000, C257S690000
Reexamination Certificate
active
06489672
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrostatic discharge (ESD) protections, and more particularly, to an integrated circuit (IC) package architecture with ESD protection in which the support bars or tie bars of the lead frame are arranged proximate to no-connect pins so that the ESD robustness of the IC package can be enhanced and the structural complexity of the same can be simplified.
2. Description of Related Art
Electrostatic discharge (ESD) is a movement of static electricity from a nonconductive surface, which usually causes damage to the semiconductors and various other circuit components in IC packages. A person walking on a carpet, for instance, can carry an amount of electrostatic charge up to several thousands of volts under high relative humidity (RH) conditions and over 10,000 volts under low relative humidity conditions. If such a person touches an IC package by hand, the electrostaticity on his/her body is instantaneously discharged via the pins of the IC package to the enclosed IC chip, thus causing ESD damage to the internal circuit of the IC chip. The ESD damage is particularly common and severe on CMOS (complementary metal-oxide semiconductor) IC devices.
To protect IC packages against ESD damage, various solutions have been proposed. One solution suggests the provision of an ESD protection circuit between the internal circuit of the IC chip and each of the bonding pads.
FIG. 1
shows a conventional IC package architecture with ESD protection circuit. As shown, the IC package includes an IC chip on which an internal circuit
20
and a plurality of bonding pads
11
,
13
,
15
are formed. Further, the IC package includes a plurality of pins
10
,
12
,
14
,
16
,
17
,
18
,
19
on its periphery. Of these, pill
10
is a power pin (V
DD
/V
SS
) which is internally connected via a bonding wire
100
to the bonding pad
11
. Pin
12
is an I/O pin, which is internally connected via a bonding wire
120
to the bonding pad
13
. Pin
14
is an input pin, which is internally connected via a bonding wire
140
to the bonding pad
15
. Pins
16
,
17
,
18
,
19
are not wired and thus are referred to as “no-connect pins”. To prevent ESD current from flowing via the bonding pads
11
,
13
,
15
into the internal circuit
20
, each of the bonding pads
11
,
13
,
15
is connected to an ESD protection circuit (not shown).
One goal in the IC packaging technology is to provide a larger number of pins with a smaller pitch on a single package for high packing density of the pins on the IC package. Since the IC package is very small in size, the increased number of pins will cause the gap between two adjacent pins, as indicated by the reference numeral G in
FIG. 1
between the pins
14
and
19
, to be further reduced in dimension. The reduction in the gap, however leads to a new problem in the ESD protection for the IC package. This problem is described in the paper, “New Failure Mechanism due to Non-Wired Pin ESD Stressing”, by Matsumoto et al. and published in the 1994 EOS/ESD Symposium, pp. 90-95. This paper reveals the fact that, when a human body model (HBM) ESD pulse is repeatedly applied to a certain no-connect pin on the IC package, any of its two neighboring pins, if wired to the internal circuit, become particularly vulnerable to ESD stress. This is because the electric charge from the ESD stress accumulates in the resin around the no-connect pin, resulting in a large potential difference between the no-connect pin and its neighboring pins that causes the neighboring pins to be vulnerable to ESD stress. In the case of
FIG. 1
, for example, assume that the input pin
14
is able to withstand a maximum of ESD stress of 3 kV (kilovolt). When an ESD stress of 1.5 kV is applied to the no-connect pin
19
, the electric charge from it will accumulate in the resin around the no-connect pin
19
, eventually resulting in a large potential difference between the no-connect pin
19
and the input pin
14
. When this potential difference reaches a large enough level. it can cause an ESD current (i.e., arc) to flow across the gap G to the neighboring input pin
14
. In such an event, this END current then flows from the input pin
14
via the bonding wire
140
and the bonding pad
15
to the internal circuit
20
. thus resulting in ESD damage to those components that are wired to the input pin
14
. In other words. when an ESD stress of 3 kV is applied directly to the input pin
14
, the components in the internal circuit
20
that are wired to the pin
14
are not damaged; however, the application of an ESD stress of only 1.5 kV (which is considerably lower than 3 kV) to the neighboring no-connect pin
19
can cause ESD damage to those components that are wired to the input pin
14
.
Early types of IC packages include only a small number of pins on them, so the above-mentioned ESD problem hardly ever occurred. However, newer types of IC packages, such as QFP (quad flat packages), MQFP, TQFP, and the like, usually come with more than one hundred pins that are packed in plastic or resin compounds. With such a large number of pins on a small-size IC package, the above-mentioned ESD problem due to the proximate arrangement of the pins becomes a serious consideration. One conventional solution to this problem is to increase the ESD robustness of the input and I/O pins of the IC package to a higher level, for example from 2 kV to 4-5 kV. This scheme can protect the input and I/O pins of the IC package against ESD damage when any one of its neighboring no-connect pins is subjected to an ESD stress of 2 kV. One drawback to this solution, however, is that the ESD protection circuit needed to provide such a level of ESD robustness takes up additional layout area on the IC chip, thus increasing the chip size.
In the package of IC chip, each of the active pins (including input pins, output pins, input/output pins, and power pins other than the no-connect pins) is electrically connected via a bonding, pad to an ESD protection circuit. Generally speaking, among these active pins, the power pins (i.e., those pins that are connected to V
DD
/V
SS
) have the highest ESD robustness since the power pins are connected to either the power bus V
DD
or the power bus V
SS
, which is connected to associated ESD protection circuits. In addition, a capacitance of about 1 nF (nanofarad) to 10 nF exists between the N-well and P-well; it is capable of absorbing a great amount of the energy from the ESD stress. The I/O pins and the output pins are next to the power pins in ESD robustness, and the input pins have the weakest ESD robustness among the active pins. This is because the I/O pins and output pins are usually connected to a bulk output buffer, while the input pins are not. The output buffer can serve as part of the ESD protection circuit for the I/O pins and output pins, thus allowing the I/O pins and output pins to be higher in ESD protection level than the input pins.
FIGS. 2A and 2B
are schematic diagrams used to depict two conventional IC package architectures. Referring first to
FIG. 2A
, the IC package shown here includes an IC chip
158
having a plurality of bonding pads
142
,
144
,
146
,
148
formed thereon. Furthermore, the IC package includes a plurality of pins
130
,
132
,
134
,
136
,
138
,
140
, which are respectively assigned as a V
SS
power pin, an input pin, a first no-connect pin, a V
DD
power pin, a second no-connect pin, and an I/O pin. The V
SS
power pin
130
, the input pin
132
, the V
DD
power pin
136
, and the I/O pin
140
are wired respectively via a plurality of bonding wires
150
,
152
,
154
,
156
to the bonding pads
142
,
144
,
146
,
148
on the IC chip
158
so as to be functionally connected to the internal circuit of the IC chip
158
. The first and second no-connect pins
134
,
138
are unwired.
Referring further to
FIG. 2B
, the IC package shown here includes an IC chip
188
having a plurality of bonding pads
172
,
174
,
176
,
178
formed thereon. Further, the IC package incl
Cao Phat X.
Winbond Electronics Corp.
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