Integrated circuit package and fabricating method thereof

Details Integrated circuit package and fabricating method thereof Integrated circuit package and fabricating method thereof

2010-01-26

2010-11-09

Menz, Douglas M (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S106000

Reexamination Certificate

active

07829388

ABSTRACT:
The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.

REFERENCES:
patent: 6201300 (2001-03-01), Tseng et al.
patent: 6265771 (2001-07-01), Ference et al.
patent: 7573131 (2009-08-01), Cui et al.
patent: 2006/0131735 (2006-06-01), Ong et al.

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