Integrated circuit package

Details Integrated circuit package Integrated circuit package

2003-03-12

2004-05-11

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S778000

Reexamination Certificate

active

06734544

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and more particularly to an integrated circuit package.
BACKGROUND
Integrated circuits (IC's) are made up of devices such as transistors and diodes and elements such as resistors and capacitors linked together by conductive connections to form one or more functional circuits. IC's are typically formed in a rectangular piece of silicon called a chip or die. Silicon dice can be formed in a wafer of silicon. A wafer is a sheet of silicon with a surface that is subject to a series of fabrication steps to form a pattern of identical IC's. The IC's are separated from each other by a repeating rectangular pattern of scribe lines, also called saw lines, in the surface of the wafer that serve as boundaries between the dice. One IC is formed in each die. At a late stage in a fabrication process the dice are diced (cut apart) from the wafer along the scribe lines and each die is bonded to a substrate to form an IC package.
A substrate is a relatively flat and rigid structure that provides mechanical support for the die in the IC package, transmits input/output (I/O) signals to and from the IC in the die, and also transfers heat that is generated during the operation of the IC. The substrate may also be called a carrier. The substrate includes conductive leads connected to respective bonding pads on the die so that the IC may exchange I/O signals with other circuits in the IC package and circuits connected to the IC package. Additional elements such as resistors and capacitors that are not readily included in the IC may be attached to the IC package. The IC package may be applied to a circuit board assembly that comprises systems of interconnected IC packages to form an electronic device such as a computer or a cellular phone.
One method of bonding a die to a substrate in an IC package is called a flip-chip bonding method. One version of the flip-chip bonding method is formally known as the controlled collapse chip connection or C4 method. In the flip-chip bonding method solder bumps are placed on bonding pads on the dice while they are connected together in the wafer. A reflow procedure is carried out to modify the shape of the bumps and then the wafer is diced to separate the dice. Each die is then turned over, or flipped, and aligned with a corresponding pattern of bonding pads or solder bumps on a substrate. A second reflow procedure is carried out to join the bumps to form a series of solder columns between the die and the substrate. The solder columns serve as conductive connections or leads between an IC in the die and the substrate through which I/O signals are transmitted. An epoxy underfill is then added between the die and the substrate, surrounding the solder columns. A fillet is formed of epoxy near the edges of the die and the epoxy is then cured to finish the fabrication of the IC package.
Most IC packages are tested under simulated operating conditions before being shipped to a customer. The test includes a thermal cycling of the IC package; the IC package is put in a furnace and the temperature of the furnace is raised and lowered in a cycle to simulate temperatures that may be encountered by the IC package in its normal operation. Stresses develop in the IC package due to different coefficients of thermal expansion of the substrate, the epoxy, and the die. The thermal cycling causes shear stresses that lead to cracks in a nitride surface layer in the die, and these cracks can propagate to open metal vias and lift metal connections in the die. In addition, the epoxy underfill includes hard particles that cause bullet holes and cracks in the die when subject to compressive stresses during the thermal cycling. Such cracking leads to a reliability failure of the IC package.
There remains a need for an IC package and ways of fabricating the IC package to reduce the above-mentioned problems. For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention an integrated circuit is formed in a die having an edge, and a plurality of non-I/O columns are bonded between a substrate and the die a selected distance from the edge of the die. According to another embodiment of the present invention an integrated circuit is formed in a die having an edge, deformable adhesive bumps are placed on the die in a high strain region of the die and on a surface of a substrate, the deformable adhesive bumps are aligned, and the die is bonded to the substrate by reforming the deformable adhesive bumps into a plurality of columns bonded between the substrate and the die to reduce strain in the die.


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