Integrated circuit package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257690, 257784, 257786, H01L 2348

Patent

active

057010323

ABSTRACT:
An integrated circuit package for housing an integrated circuit (IC) chip and providing electrical connectivity of data signals and voltage signals between the IC chip and an electronic component includes a substrate, an IC chip affixed to the substrate and at least three conductive layers on the substrate. The three conductive layers include at least a first voltage layer adjacent to the substrate for providing a first reference voltage signal (i.e., ground) to the IC chip, a second voltage layer for providing a second reference voltage signal (i.e., power) to the IC chip, and a signal layer. To maximize speed and minimize complexing all of the data signals to the IC chip are routed on the signal layer. The power and ground layers are closely coupled and separated by a dielectric layer having a relatively high dielectric constant for providing significant decoupling capacitance. A low dielectric layer is provided for separating the power layer from the signal layer. A plurality of electrical connections interconnect bonding pads on the IC chip with the electronic component (e.g., a PCB) by way of at least one of the conductive layers.

REFERENCES:
patent: 3617817 (1971-11-01), Kawakatsu et al.
patent: 4499149 (1985-02-01), Berger
patent: 4608592 (1986-08-01), Miyamoto
patent: 4996097 (1991-02-01), Fischer
patent: 5034801 (1991-07-01), Fischer
patent: 5132778 (1992-07-01), Juskey et al.
patent: 5136366 (1992-08-01), Worp et al.
patent: 5153385 (1992-10-01), Juskey et al.
patent: 5166772 (1992-11-01), Soldner et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5218759 (1993-06-01), Juskey et al.
patent: 5220489 (1993-06-01), Barreto et al.
patent: 5239198 (1993-08-01), Lin et al.
patent: 5284287 (1994-02-01), Wilson et al.
patent: 5285352 (1994-02-01), Pastore et al.
patent: 5293069 (1994-03-01), Kato et al.
patent: 5296738 (1994-03-01), Freyman et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5376588 (1994-12-01), Pendse
patent: 5394009 (1995-02-01), Loo
patent: 5397917 (1995-03-01), Ommen et al.
patent: 5525834 (1996-06-01), Fischer et al.
"Thin Film Module," IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989, New York, pp. 135-138.
"Mounting Open-Via Chip-Carriers (for 100 to 300, input/output i.c.)", 4th IEEE/CHMT European IEMTS, Jun. 13-15, 1988, Neuilly Sur Seine, France, pp.34-36, C.M. Val et al.
"New BGA Design Concept," IBM Technical Disclosure Bulletin, vol. 37, No. 6A, Jun. 1994 New York U.S., pp. 23-24.
"Leistung Richtig Verpackt," Elektronik, vol. 41, No. 110, May 12, 1992, G. Warson et al., pp. 92-96.
"An 820 Pin PGA For Ultralarge-Scale BiCMOS Device," IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 16, No. 8, Dec. 1993, Y. Hiruta et al., pp. 893-901.
"Chip Attachment to Tape and Cable," IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982, J.C. Edwards, pp. 1954-1956.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integrated circuit package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit package will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1804220

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.