Integrated circuit package

Details Integrated circuit package Integrated circuit package

1990-02-15

1991-05-14

Hille, Rolf

357 51, 357 71, H01L 2312, H01L 2314

Patent

active

050160877

ABSTRACT:
Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.
Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.
The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).
Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.
Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.
At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

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