Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-06-23
2001-10-23
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S270000, C327S281000
Reexamination Certificate
active
06307417
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to digital integrated circuit devices having output buffers therein for driving capacitive loads and methods of operating same.
BACKGROUND OF THE INVENTION
CMOS integrated circuits typically include inverting buffer circuits therein for driving on-chip and off-chip loads. As illustrated by
FIG. 1
, a conventional CMOS inverting buffer circuit includes a PMOS pull-up transistor T
1
and an NMOS pull-down transistor T
2
which are electrically connected in series between a power supply voltage (Vcc) and a ground or negative reference voltage (Vss).
Unfortunately, although the buffer circuit of
FIG. 1
can be designed to switch at relatively high speeds, it requires a large amount current from its power supply when switching a capacitive load C
L
from Vss to Vcc and then back to Vss. For example, a large total charge Q=C
L
(Vcc) is required from the power supply to switch each capacitive load C
L
through an entire pull-up and pull-down cycle. Accordingly, if an integrated circuit has a large number of buffer circuits therein that frequently switch appreciable loads, the amount of switching current required from the power supply may be substantial.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit devices and methods of operating same.
It is another object of the present invention to provide integrated circuit devices having substantially reduced power consumption requirements and methods of operating same.
It is still another object of the present invention to provide integrated circuit devices containing improved buffers therein with enhanced energy efficiency characteristics, and methods of operating same.
These and other objects, advantages and features of the present invention are provided by preferred integrated circuit devices that according to one embodiment of the present invention comprise an integrated circuit substrate, a plurality of output buffers in the substrate that drive respective loads, a first supplemental voltage supply pad on the substrate, a plurality of first switches and at least one external capacitor that is electrically coupled to the first supplemental voltage supply pad. This external capacitor acts as a supplemental voltage supply to maintain the first supplemental voltage supply pad at an intermediate voltage. According to a preferred aspect of this embodiment, each of the first switches is electrically coupled in series between an output of a respective one of the plurality of output buffers and the first supplemental voltage supply pad. Because each output buffer may comprise a pull-up switch and a pull-down switch, each output buffer and respective first switch may be treated as at least three independently controllable switches: a switch to pull the output towards a first intermediate voltage at the first supplemental voltage supply pad, a switch to pull the output towards a power supply voltage Vcc and a switch to pull the output towards a ground reference voltage Vss.
In particular, during operation of a preferred device, the first switch may be closed (turned on) to transfer charge from the at least one external capacitor (e.g., 1 pF) to a capacitive load (e.g., 100 pF) which is electrically connected to an output of a respective output buffer. This capacitive load may be formed by an “on-chip” device and/or “off-chip” device, for example. This transfer of charge occurs at the beginning of a pull-up time interval as the voltage across the capacitive load is being driven from a ground reference voltage Vss to a first intermediate voltage V
1
(where Vss<V
1
<Vcc) while the pull-up and pull-down switches of the respective output buffer are both maintained in a high impedance state (turned off). Then, after this “forward” charge transfer to the load, the first switch may be opened (turned off). The pull-up switch of the respective output buffer can then be closed (turned on) in a pull-up mode to drive the corresponding capacitive load from the first intermediate voltage V
1
to the power supply voltage Vcc using current supplied by the power supply. The pull-up switch remains closed (turned on) as long as a high output voltage is required.
Then, when it is required to switch the output from a high level to a low level, the pull-up switch is turned off and the first switch is turned on again to transfer charge back from the capacitive load to the at least one external capacitor and thereby pull the output towards the first intermediate voltage on the supplemental voltage supply pad. This “reverse” transfer of charge preferably occurs at the beginning of a pull-down time interval as the voltage across the capacitive load is being driven from the power supply voltage Vcc to a second intermediate voltage V
2
(where Vss<V
2
<Vcc). This “reverse” charge transfer from the capacitive load to the supplemental voltage supply essentially replaces the “forward” charge transferred from the supplemental voltage supply to the capacitive load during the first portion of the pull-up time interval. Then, after this reverse charge transfer from the load, the first switch is turned off (opened) and the respective output buffer is placed in a pull-down mode by turning the pull-down switch on to thereby drive the output from the intermediate voltage V
2
to the ground (or negative) reference voltage Vss.
Based on this embodiment of the present invention, the overall power consumed by an output buffer when driving a capacitive load through a pull-up/pull-down cycle can be reduced considerably by essentially “recycling” the charge initially passed from the at least one external capacitor to the load during the forward charge transfer, as charge returned to the at least one external capacitor during the reverse charge transfer. This means that significant portions of each pull-up/pull-down cycle do not consume power from the power supply, which makes the present invention particularly suited for battery powered devices. However, additional delay may be incurred because the total time required to perform the initial forward charge transfer and also pull-up the load from V
1
→Vcc is typically greater than the amount of time it would otherwise take for the output driver to drive the capacitive load directly from Vss to Vcc. The same is true for the pull-down portion of each cycle. To improve its “start-up” characteristics, the above-described embodiment may also include a pair of external capacitors that are electrically connected in series between the power supply voltage Vcc and the ground reference voltage Vss and electrically connected together at the first supplemental voltage supply pad.
According to another embodiment of the present invention, an integrated circuit device is provided that comprises an integrated circuit substrate, an output buffer in the substrate, first and second supplemental voltage supply pads on the substrate, first and second switches which each have an input electrically connected to an output of the output buffer, and first and second external capacitors which are electrically connected in series between Vcc and Vss and together at an intermediate reference node. The outputs of the first and second switches are also electrically connected to the first and second supplemental voltage supply pads. In addition, first and second external inductors are preferably provided. The first inductor is electrically connected in series between the intermediate reference node and the first supplemental voltage supply pad and the second inductor is electrically connected in series between the intermediate reference node and the second supplemental voltage supply pad. The first and second switches may be provided as a single CMOS transmission gates, for example, or the first and second switches may comprise separately controllable NMOS and PMOS transistors, respectively. Other types of switches may also be used.
According to this embodiment of the present inve
Lam Tuan T.
Myers Bigel & Sibley & Sajovec
Nguyen Hiep
LandOfFree
Integrated circuit output buffers having reduced power... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit output buffers having reduced power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit output buffers having reduced power... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2605646