Integrated circuit offset voltage adjustment

Details Integrated circuit offset voltage adjustment Integrated circuit offset voltage adjustment

1986-05-22

1988-01-05

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including differential amplifier

330296, H03F 345

Patent

active

047178884

ABSTRACT:
An integrated circuit disposed in a package having a plurality of electrical interconnection leads, a first interconnection lead being adapted to receive an input signal during a normal operating mode of the integrated circuit. The integrated circuit comprises a supply voltage bus coupled to a second interconnection lead and fed by a reference potential and a differential amplifier comprising a pair of emitter-coupled transistors. The differential amplifier has a nominal offset voltage which is a function of a nominal resistance coupled between the collector electrode of a first one of the pair of emitter-coupled transistors and the reference potential. The nominal resistance is provided by a plurality of serially-coupled resistors. A network is coupled between the supply voltage bus and the collector electrode of the first transistor, such network comprising: a first resistor nominally electrically decoupled from between the supply voltage bus and said collector electrode; a switch element, responsive to a programming signal applied across the first and second interconnection leads during a programming mode of the integrated circuit, for electrically coupling the first resistor between the supply voltage bus and said collector electrode to change the offset voltage from the nominal offset voltage by a predetermined amount; and a control element operable during the programming mode to electrically couple the switch element to the first interconnection lead, and operable during the normal operating mode to electrically decouple the switch element from the first interconnection lead.

REFERENCES:
patent: 3870967 (1975-03-01), Wisseman
patent: 4045746 (1977-08-01), Wheatley, Jr.
patent: 4131844 (1978-12-01), Comer
patent: 4138671 (1979-02-01), Comer et al.
patent: 4207536 (1980-06-01), Lewis
Eroi, "A Precision Trim Technique for Monolithic Analog Circuits," 1975 IEEE International Solid-State Circuits Conference, Feb. 14, 1975, pp. 192, 193.
"Op AMP Has low Offset Voltage," Electronics, Aug. 28, 1980, pp. 288-290.

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