Integrated circuit non-etch technique for forming vias in a semi

Details Integrated circuit non-etch technique for forming vias in a semi Integrated circuit non-etch technique for forming vias in a semi

1996-07-25

1998-10-20

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Groove

257618, 257620, 257 48, 437226, 437203, H01L 21463, H01L 2178

Patent

active

058250760

ABSTRACT:
A semiconductor wafer and a method of forming vias in a semiconductor wafer having opposite first and second planar surfaces and predetermined thickness includes forming a plurality of first channels of first predetermined depth along a first direction in the first planar surface of the semiconductor wafer and forming a plurality of second channels of second predetermined depth along a second direction in the second planar surface of the semiconductor wafer. The first and second predetermined depths of the channels are selected such that vias are formed through the semiconductor wafer. The channels may be formed by saw cutting or scribing the planar surfaces of the semiconductor wafer. A plurality of circuit devices may be formed on the first planar surface of the semiconductor wafer prior to forming the plurality of first and second channels. A metallic layer is deposited within the vias and on the first and second planar surfaces to provide electrical connection between the circuit devices and the second planar surface of the semiconductor wafer through the vias.

REFERENCES:
patent: 4839300 (1989-06-01), Kawahara et al.
patent: 5314844 (1994-05-01), Imamura
patent: 5532174 (1996-07-01), Corrigan

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