Integrated circuit multiport memory having serial access bit mas

Details Integrated circuit multiport memory having serial access bit mas Integrated circuit multiport memory having serial access bit mas

1995-09-14

1998-07-28

Swann, Tod R.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395431, 395164, 345191, 345197, 345188, 36518901, 36518912, 36523015, 36523009, 364DIG1, G06F 1300

Patent

active

057873119

ABSTRACT:
An integrated circuit (IC) architecture includes a bit mask register (BMR) and a serial access memory (SAM) which share address decode and clock circuitry within a multiport random access memory chip. The integrated circuit also includes a random access memory and circuitry for performing a bit masked transfer between the serial access memory and the random access memory. Mask data may be clocked into the bit mask register, which may be cleared upon completion of a data transfer between the random access memory and the serial access memory. The mask data may also be inverted upon being transferred between the random access memory and the bit mask register. This architecture provides CLEAR and TRUE or COMPLEMENT masked transfer output ability in the BMR, and has utility in real-time video windowing in memory mapped computer graphics.

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"Datacube Proposal For One-Megabit Triple-Port Video Ram", J. Dunn; Datacube, Inc. Feb. 28, 1989.
Nakane, Masayoshi and Kaoru Tokushige; "Video Ram Chips Designed for Computer Graphics"; Nov. 1987; pp. 28 through 31; Journal of Electronic Engineering? (JEE).

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