Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure
Reexamination Certificate
1999-04-30
2001-01-23
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Integrated structure
C327S564000
Reexamination Certificate
active
06177833
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit modules, and more particularly to integrated circuit modules having reduced impedance and a method for providing such modules.
BACKGROUND OF THE INVENTION
Requirements of modern computers increasingly burden the design of their memory modules due to increased output driver current and expected voltage slew rate.
During operation of the computer as each required circuit switches on, an output current is applied to its respective I/O pin or pad and, in turn, this current must flow from the driver power supply associated with the circuit being turned on. Consequently, where a large number of drivers switch simultaneously or at high frequency, a DC or AC shift in supply potential can occur which degrades the noise margins on the chip. This becomes more significant as power supply voltages decrease. Hence it is of importance to decrease the impedance of circuit modules.
In a paper entitled “Ground Bounce Control in CMOS Circuits” appearing in the “1988 IEEE International Solid State Circuits Conference Transactions”, the problem of ground noise or bounce, due to the variation of the chip ground relative to the external ground, was discussed together with a proposed solution. This solution required having a control voltage source, tailored to the process creating the circuit, be created to regulate the charge/discharge rate of a series transistor in the output buffer and thereby equalize the delay, speed, rise/fall time and ground bounce of the CMOS output buffers thus requiring the faster element be slowed down. Further, this proposed solution is process dependent and cannot, for a number of practical purposes, be used in production.
U.S. Pat. No. 5,317,206 is directed to an attempt to stabilize voltage bounce within a circuit and does this by adding delay elements to the circuit. These delay elements, arranged to decrease the rising speed of the voltage at the circuit output, reduce the voltage noise but do so by sacrificing circuit speed.
Similarly U.S. Pat. No. 5,315,172 adds a pair of transistors serially connected between the voltage supply and ground with their common terminal connected to the circuit output so that, when either one of this serially connected pair is turned on, a slower rate of charge or discharge of the output occurs. This reduces the time rate of change of current through the circuit inductance and thereby reduces the voltage noise or bounce but again does do by sacrificing circuit speed.
U.S. Pat. No. 5,568,081 teaches the use of a variable slew rate control circuit for automatically adjusting the rate at which a node is driven to a voltage once again by sacrificing circuit speed.
As a practical solution, the semiconductor industry will only accept circuit changes that can be easily and inexpensively produced without sacrificing circuit speed or significantly impacting other circuit performance criteria. The present invention overcomes the above described problems without requiring additional circuit elements that impact circuit performance or speed.
SUMMARY OF THE INVENTION
A circuit module of reduced impedance, and a method for providing the same, utilizes an integrated circuit module having a chip architecture providing a given circuit, such as a memory circuit and a plurality of off-chip drivers such that, when the module is configured for operation with less than the total number available drivers, some drivers and their output pads are in excess, and in accordance with the invention, at least one of the excess drivers and its associated output pad are connected to the power terminals to provide at least one additional power voltage path in parallel with the power paths in the operational drivers to thereby reduce module impedance.
The method includes connecting one or more of its excess drivers and their output pads to the power terminals for conduction through at least portions of these drivers thereby providing additional power paths in parallel with the previously existing power paths in the module. Hence, this reduction in module impedance is achieved by forcing excess drivers and their output pads to operate as additional power paths in parallel to the usual power paths in the chip.
In the preferred embodiment, substantially all of the excess drivers and their output pads are utilized to provide impedance lowering, additional power paths. Moreover, one half of the excess drivers and their output pads are preferably connected across the power terminals of the chip for conduction in a first direction whereas the other half are connected to the power terminals to provide conduction in the opposite direction.
Accordingly, it is an object of the present invention to provide a circuit module having reduced impedance.
It is another object of the invention to provide a circuit module having added power paths to thereby reduce module impedance.
It is a further object of the invention to provide a method of making a module having reduced impedance by enhancement of a present chip design to economically add power paths in the chip during fabrication.
It is a still further object of the invention to utilize excess output pads in a given semiconductor chip to facilitate the provision of additional power paths therein.
These and other objects and features of the present invention will become further apparent from the following description taken in conjunction with the drawings.
REFERENCES:
patent: 5311081 (1994-05-01), Donaldson et al.
patent: 5444311 (1995-08-01), Imai et al.
patent: 5508906 (1996-04-01), Nelli et al.
patent: 5568081 (1996-10-01), Lui et al.
patent: 5675298 (1997-10-01), Bhagwan et al.
Gabric John A.
Roberge Michael A.
Thoma Endre P.
Callahan Timothy P.
International Business Machine Corp.
Luu An T.
Thornton David R.
Thornton & Thornton
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