Integrated circuit models having associated timing exception...

Details Integrated circuit models having associated timing exception... Integrated circuit models having associated timing exception...

1999-09-13

2004-01-13

Thomson, W. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S020000, C703S019000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06678644

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to integrated circuit modeling having timing information associated therewith for use with EDA systems for the design of integrated circuit devices.
2. Related Art
Rapid growth in the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the integrated circuit design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or “cells.” These designs are much too large for a circuit designer or even an engineering team of designers to manage effectively manually. To automate the design and fabrication of integrated circuit devices, the field of electronic design automation (EDA) has been developed which uses computer aided design (CAD) tools and systems.
Typically, CAD tools function in part by decomposing the overall desired behavior of the integrated circuit into simpler functions which can be represented as functional cells by the CAD tool. The CAD tool generates netlists including cells, logic gates and connections between them which perform the desired circuit behavior. Netlists can represent the integrated circuit in different levels of abstraction depending on the CAD function being performed, such as the behavior level, the structural level and the gate level. However, the high level design (HDL) description is typically the starting point for CAD tools because the HDL description file describes the behavior of the integrated circuit.
FIG. 1
illustrates a prior art EDA process
100
. An HDL description
101
of an integrated circuit is received by a logic synthesis process
102
. Process
102
first generates a technology independent netlist (including cells) based on the HDL description
101
and then generates a technology dependent netlist (including gates) based on a specified process technology library
103
. The technology specific library
103
includes specific information regarding the cells of the selected process technology.
Optimization processes
104
are then applied to the technology dependent netlist so that specified design constraints
105
(e.g., area constraints and timing, power and other performance related constraints) can be maintained in the resultant design. Optimization
104
is the process of mapping one representation of functionality for an electronic circuit to another. The representation may be in terms of a circuit netlist (an abstract interconnection of electronic components), a circuit layout (an interconnection of components and their associated physical placement and wiring), or an abstract functional description which simply describes the function the circuit should perform without fully specifying circuit details. In general, optimization attempts to improve some aspect of the functionality of a circuit, e.g., its speed, its size, its power consumption, or some other circuit parameter. The goal of the optimization processes
104
is to select a functionally equivalent cell or group of cells that can be used to replace an existing cell where the replacement reduces the area of the integrated circuit or improves its performance (e.g., speed, power dissipation, etc.). The “Design Compiler,” which is commercially available from Synopsys, Inc. of Mountain View, Calif., is an example of an automated circuit optimizer
104
.
Circuit simulation
106
of
FIG. 1
is used to determine if the modifications performed by the optimization process satisfy the given design constraints
105
. Circuit simulation
106
can also be used to test if the netlist operates in the proper logical manner. At step
108
of
FIG. 1
, if the netlist satisfies the given design constraints
105
and logical simulation verifies, it is used to fabricate a physical integrated circuit device. Step
108
typically includes automatic coarse and fine placement processes where the cells of the netlist are spatially placed in the substrate area. Then, interconnections between the cells are routed in an automatic routing process.
The steps outlined in process
100
can be very process intensive thereby consuming large amounts of computer time and computer resources. For this reason, it is typical for large integrated circuit designs to be broken down into separate circuit blocks with each block independently being subjected to one or more of the steps of process
100
. “Characterization” refers to the process of setting up distinct circuit blocks of a large circuit design to be optimized independently, outside of the whole integrated circuit design. For instance, assume a circuit design, E, contains circuit blocks A, B, C, and D. Circuit E has specified timing constraints and timing exceptions. Characterization automatically generates timing constraints and exceptions which are appropriate for the optimization of blocks A, B, C and D, independently. When optimizing the blocks using characterization, the optimization tool
104
(
FIG. 1
) need only load and process one block at a time. This decreases the demand of the tool on the computer resources. After the blocks have been optimized, they are then re-assembled back into circuit E. One example of the characterization described above is the “characterize” command found in the above referenced Design Compiler tool from Synopsys, Inc. of Mountain View, Calif.
Modeling is another tool used in EDA processes to reduce the demand on computer resources when designing integrated circuits. Modeling represents a circuit block in a more compact form so that it requires less computer memory resources to represent and also so that it requires less processor time to process. Usually, models achieve their smaller memory requirements by omitting details about the original block in the model. Because details are omitted from them, models cannot be used as a universal replacement for a circuit block. Usually models can only be used for very specific purposes. Prior art models contain a limited amount of information about the circuit block they replace. For instance, prior art models contain the circuit block size, the name and physical position of the pins of the circuit block, the pin's imposed electrical capacitance, the pin's imposed electrical current (drive), the arrival time at a circuit block's output and the required time at a circuit block's input. Although useful for some applications, the above described models do not model timing exceptions and therefore these models are not appropriate for use in general applications such circuit optimization.
The “model” command of the Design Compiler from Synopsys, Inc. and the “extract_model” command of PrimeTime from Synopsys, Inc. create models from circuit blocks. U.S. Pat. No. 5,790,830, issued Aug. 4, 1998, by Russell B. Segal and entitled “Extracting Accurate and Efficient Timing Models of Latch-Based Designs” describes one form of modeling. These models can be used in a circuit to evaluate the timing. These models are appropriate for replacing prepackaged circuit blocks which are self contained. However, these models are not appropriate to general applications such as use in optimization because, among other shortcomings, they do not model timing exceptions.
Accordingly, what is needed is a method and system for providing a more effective circuit block model. What is needed further is a more effective and efficient optimization process. The present invention provides these advantages. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
SUMMARY OF THE INVENTION
Embodiments of the present invention as described herein are drawn to solutions to problems posed by the optimization and analysis of large circuits. When circuits get large, they place a large burden on optimization and analysis tools which try to process them. In particular, the tools

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