Integrated circuit micro-module

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257S415000, C257S700000, C257S713000, C257S723000, C257S724000, C257SE21499, C257SE21506, C257SE21536, C257SE21705

Reexamination Certificate

active

07843056

ABSTRACT:
In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques.

REFERENCES:
patent: 6734569 (2004-05-01), Appelt et al.
patent: 6911355 (2005-06-01), Farnworth et al.
patent: 7232733 (2007-06-01), Lotfi et al.
patent: 7473579 (2009-01-01), Sharifi et al.
patent: 2003/0206680 (2003-11-01), Bakir et al.
patent: 2007/0111385 (2007-05-01), Magerlein et al.
patent: 2007/0132086 (2007-06-01), Agraharam et al.
patent: 2007/0181979 (2007-08-01), Beer et al.
patent: 2008/0116564 (2008-05-01), Yang et al.
patent: 2008/0157336 (2008-07-01), Yang
patent: 2008/0174020 (2008-07-01), Ga
patent: 2008/0201944 (2008-08-01), Sakamoto et al.
patent: 2009/0159875 (2009-06-01), Chabinyc et al.
patent: 2010/0127375 (2010-05-01), Galera et al.
Yang et al. “3D Multilayer Integration and Packaging or Organic/Paper Low-cost Substrates for RF and Wireless Applications.” IEEE 2007.
Pieters et al. “3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking.” 7thInternational Conference on Electronics Packaging Technology, 2006.
Tummala et al. “Microsystems Packaging from Milli to Microscale to Nanoscale.” IEEE 2004.
Tummala, Rao R. “Packaging: Past, Present and Future.” 6thInternational Conference on Electronic Packaging Technology, 2005.
Lim, Sung Kyu. “Physical Design for 3D Systems on Package.” IEEE Design & Test of Computers, 2005.
Yoon et al. “Polymer Embedded Module for SiP Application.” 2004 Electronics Packaging Technology Conference.
Tummala, Rao R. “SOP: What Is It and Why? A New Microsystem-Integration Technology Paradigm—Moore's Law for System Integration of Miniaturized Convergent Systems of the Next Decade.” IEEE Transactions on Advanced Packaging, vol. 27, No. 2, May 2004.
Souriau et al. “Wafer Level Processing of 3D System in Package for RF and Data Applications.” 2005 Electronic Components and Technology Conference.
Tuominen, Risto. “IMB Technology for Embedding Active Components into a Substrate.” SEMICON Europa, Munich, Germany. Apr. 4, 2006.
Keser et al. “Advanced Packaging: the Redistributed Chip Package.” IEEE Transactions on Advanced Packaging, vol. 31, No. 1, Feb. 2008.
Knickerbocker et al. “3-D Silicon Integration Silicon Packaging Technology Using Silicon Through-Vias.” IEEE Journal of Solid State Circuits, vol. 41, No. 8, Aug. 2006.
Sharifi et al. “Self-Aligned Wafer-Level Integration Technology with High-Density Interconnects Embedded Passives.” IEEE Transactions on Advanced Packaging, vol. 30, No. 1, Feb. 2007.
JMD's Multi-Layer Organic (MLO) technology, downloaded Nov. 2007 from www.jacketmicro.com/technology/.
International Search Report dated Aug. 25, 2010 from International Patent Application No. PCT/US2010/020555.
Written Opinion dated Aug. 25, 2010 from International Patent Application No. PCT/US2010/020555.
Notice of Allowance dated Sep. 10, 2010 from U.S. Appl. No. 12/479,713.
Adler, Micheal. “GE High Density Interconnect: A Solution to the System Interconnect Problem.” Downloaded on Jul. 20, 2009 from IEEE Xplore.
Office Action dated Aug. 23, 2010 from U.S. Appl. No. 12/479,707.

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