Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2011-03-08
2011-03-08
Mulpuri, Savitri (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S415000, C257S678000, C257S700000, C257S713000, C257S720000, C257SE21499, C257SE21502, C257SE21536, C257SE21575
Reexamination Certificate
active
07902661
ABSTRACT:
Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
REFERENCES:
patent: 6218729 (2001-04-01), Zavrel, Jr. et al.
patent: 6555759 (2003-04-01), Tzanavaras et al.
patent: 6734569 (2004-05-01), Appelt et al.
patent: 6911355 (2005-06-01), Farnworth et al.
patent: 7232733 (2007-06-01), Lotfi et al.
patent: 7473579 (2009-01-01), Sharifi et al.
patent: 7589392 (2009-09-01), Shastri et al.
patent: 2003/0206680 (2003-11-01), Bakir et al.
patent: 2004/0152242 (2004-08-01), Wong
patent: 2007/0090533 (2007-04-01), Haga et al.
patent: 2007/0111385 (2007-05-01), Magerlein et al.
patent: 2007/0132086 (2007-06-01), Agraharam et al.
patent: 2007/0181979 (2007-08-01), Beer et al.
patent: 2007/0227761 (2007-10-01), Tuominen et al.
patent: 2008/0079125 (2008-04-01), Lu et al.
patent: 2008/0116564 (2008-05-01), Yang et al.
patent: 2008/0157336 (2008-07-01), Yang
patent: 2008/0174020 (2008-07-01), Ga
patent: 2008/0201944 (2008-08-01), Sakamoto et al.
patent: 2009/0159875 (2009-06-01), Chabinyc et al.
patent: 2010/0013101 (2010-01-01), Hedler et al.
patent: 2010/0127375 (2010-05-01), Galera et al.
Office Action dated Aug. 23, 2010 from U.S. Appl. No. 12/479,707.
International Search Report dated Aug. 25, 2010 from International Patent Application No. PCT/US2010/020555.
Written Opinion dated Aug. 25, 2010 from International Patent Application No. PCT/US2010/020555.
Notice of Allowance dated Sep. 20, 2010 from U.S. Appl. No. 12/390,349.
Notice of Allowance dated Sep. 10, 2010 from U.S. Patent Appl. No. 12/479,713.
Tuominen, Risto. “IMB Technology for Embedding Active Components into a Substrate.” SEMICON Europa, Munich, Germany. Apr. 4, 2006.
Keser et al. “Advanced Packaging: The Redistributed Chip Package.” IEEE Transactions on Advanced Packaging, vol. 31, No. 1, Feb. 2008.
Knickerbocker et al. “3-D Silicon Integration Silicon Packaging Technology Using Silicon Through-Vias.” IEEE Journal of Solid State Circuits, vol. 41, No. 8, Aug. 2006.
Sharifi et al. “Self-Aligned Wafer-Level Integration Technology with High-Density Interconnects Embedded Passives.” IEEE Transactions on Advanced Packaging, vol. 30, No. 1, Feb. 2007.
JMD's Multi-Layer Organic (MLO) technology, downloaded Nov. 2007 from www.jacketmicro.com/technology/.
Yang et al. “3D Multilayer Integration and Packaging or Organic/Paper Low-cost Substrates for RF and Wireless Applications.” IEEE 2007.
Pieters et al. “3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking.” 7thInternational Conference on Electronics Packaging Technology, 2006.
Tummala et al. “Microsystems Packaging from Milli to Microscale to Nanoscale.” IEEE 2004.
Tummala, Rao R. “Packaging: Past, Present and Future.” 6thInternational Conference on Electronic Packaging Technology, 2005.
Lim, Sung Kyu. “Physical Design for 3D Systems on Package.” IEEE Design & Test of Computers, 2005.
Yoon et al. “Polymer Embedded Module for SiP Application.” 2004 Electronics Packaging Technology Conference.
Tummala, Rao R. “SOP: What Is It and Why? A New Microsystem-Integration Technology Paradigm—Moore's Law for System Integration of Miniaturized Convergent Systems of the Next Decade.” IEEE Transactions on Advanced Packaging, vol. 27, No. 2, May 2004.
Souriau et al. “Wafer Level Processing of 3D System in Package for RF and Data Applications.” 2005 Electronic Components and Technology Conference.
Adler, Micheal. “GE High Density Interconnect: A Solution to the System Interconnect Problem.” Downloaded on Jul. 20, 2009 from IEEE Xplore.
Notice of Allowance dated Oct. 29, 2010 from U.S. Appl. No. 12/479,707.
Notice of Allowance dated Nov. 15, 2010 from U.S. Appl. No. 12/479,709.
Notice of Allowance dated Nov. 30, 2010 from U.S. Appl. No. 12/479,715.
Deane Peter
Johnson Peter
Razouk Reda R.
Smeys Peter
Ahmadi Mohsen
Beyer Law Group LLP
Mulpuri Savitri
National Semiconductor Corporation
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