Integrated circuit micro-module

Details Integrated circuit micro-module Integrated circuit micro-module

2011-03-01

2011-03-01

Mulpuri, Savitri (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S700000, C257S713000, C257S717000, C257S718000, C257S720000, C257SE21499, C257SE21502, C257SE21506, C257SE21536, C257SE21576

Reexamination Certificate

active

07898068

ABSTRACT:
Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

REFERENCES:
patent: 6218729 (2001-04-01), Zavrel, Jr. et al.
patent: 6555759 (2003-04-01), Tzanavaras et al.
patent: 6734569 (2004-05-01), Appelt et al.
patent: 6911355 (2005-06-01), Farnworth et al.
patent: 7232733 (2007-06-01), Lotfi et al.
patent: 7473579 (2009-01-01), Sharifi et al.
patent: 7589392 (2009-09-01), Shastri et al.
patent: 2003/0206680 (2003-11-01), Bakir et al.
patent: 2004/0152242 (2004-08-01), Wong
patent: 2007/0090533 (2007-04-01), Haga et al.
patent: 2007/0111385 (2007-05-01), Magerlein et al.
patent: 2007/0132086 (2007-06-01), Agraharam et al.
patent: 2007/0181979 (2007-08-01), Beer et al.
patent: 2007/0227761 (2007-10-01), Tuominen et al.
patent: 2008/0079125 (2008-04-01), Lu et al.
patent: 2008/0116564 (2008-05-01), Yang et al.
patent: 2008/0157336 (2008-07-01), Yang
patent: 2008/0174020 (2008-07-01), Ga
patent: 2008/0201944 (2008-08-01), Sakamoto et al.
patent: 2009/0159875 (2009-06-01), Chabinyc et al.
patent: 2010/0013101 (2010-01-01), Hedler et al.
patent: 2010/0127375 (2010-05-01), Galera et al.
Tuominen, Risto. “IMB Technology for Embedding Active Components into a Substrate.” SEMICON Europa, Munich, Germany. Apr. 4, 2006.
Keser et al. “Advanced Packaging: The Redistributed Chip Package.” IEEE Transactions on Advanced Packaging, vol. 31, No. 1, Feb. 2008.
Knickerbocker et al. “3-D Silicon Integration Silicon Packaging Technology Using Silicon Through-Vias.” IEEE Journal of Solid State Circuits, vol. 41, No. 8, Aug. 2006.
Sharifi et al. “Self-Aligned Wafer-Level Integration Technology with High-Density Interconnects Embedded Passives.” IEEE Transactions on Advanced Packaging, vol. 30, No. 1, Feb. 2007.
JMD's Multi-Layer Organic (MLO) technology, downloaded Nov. 2007 from www.jacketmicro.com/technology/.
Yang et al. “3D Multilayer Integration and Packaging or Organic/Paper Low-cost Substrates for RF and Wireless Applications.” IEEE 2007.
Pieters et al. “3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking.” 7thInternational Conference on Electronics Packaging Technology, 2006.
Tummala et al. “Microsystems Packaging from Milli to Microscale to Nanoscale.” IEEE 2004.
Tummala, Rao R. “Packaging: Past, Present and Future.” 6thInternational Conference on Electronic Packaging Technology, 2005.
Lim, Sung Kyu. “Physical Design for 3D Systems on Package.” IEEE Design & Test of Computers, 2005.
Yoon et al. “Polymer Embedded Module for SiP Application.” 2004 Electronics Packaging Technology Conference.
Tummala, Rao R. “SOP: What Is It and Why? A New Microsystem-Integration Technology Paradigm—Moore's Law for System Integration of Miniaturized Convergent Systems of the Next Decade.” IEEE Transactions on Advanced Packaging, vol. 27, No. 2, May 2004.
Souriau et al. “Wafer Level Processing of 3D System in Package for RF and Data Applications.” 2005 Electronic Components and Technology Conference.
Adler, Micheal. “GE High Density Interconnect: A Solution to the System Interconnect Problem.” Downloaded on Jul. 20, 2009 from IEEE Xplore.
Office Action dated Aug. 23, 2010 from U.S. Appl. No. 12/479,707.
International Search Report dated Aug. 25, 2010 from International Patent Application No. PCT/US2010/020555.
Written Opinion dated Aug. 25. 2010 from International Patent Application No. PCT/US2010/020555.
Notice of Allowance dated Sep. 20, 2010 from U.S. Appl. No. 12/390,349.
Notice of Allowance dated Sep. 10, 2010 from U.S. Appl. No. 12/479,713.
Notice of Allowance dated Oct. 29, 2010 from U.S. Appl. No. 12/479,707.
Notice of Allowance dated Nov. 16, 2010 from U.S. Appl. No. 12/463,924.
Notice of Allowance dated Nov. 30, 2010 from U.S. Appl. No. 12/479,715.

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