Integrated circuit method for and structure with narrow line wid

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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257401, 257134, 257197, 257287, 257288, H01L 2974, H01L 310328, H01L 2976, H01L 2994

Patent

active

057738912

ABSTRACT:
In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or emitter contact 35 is formed from the second polysilicon layer 14. The gate 19 or emitter 35 is spaced from the lines 1,2 a distance approximately equal to the thickness of the second polysilicon layer 14.

REFERENCES:
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patent: 4968646 (1990-11-01), Blanchard et al.
patent: 4970177 (1990-11-01), Mizushima
patent: 5049515 (1991-09-01), Tzeng
patent: 5057899 (1991-10-01), Samata et al.
patent: 5137837 (1992-08-01), Chang et al.
patent: 5196373 (1993-03-01), Beasom
patent: 5242846 (1993-09-01), Izumi et al.
patent: 5378646 (1995-01-01), Huang et al.
S. Wolf, "Silicon Processing For The VLSI Era", vol. 2, Process Integration, pp. 214-217, 1990.

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