Integrated circuit metal oxide semiconductor transistor

Details Integrated circuit metal oxide semiconductor transistor Integrated circuit metal oxide semiconductor transistor

2003-09-11

2004-07-06

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

Reexamination Certificate

active

06759695

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit metal oxide semiconductor transistors and a method of manufacturing the same and, more particularly, to a gate replacement process conducted after high temperature treatment of the device so as to minimize diffusion of germanium in the gate dielectric material.
BACKGROUND OF THE INVENTION
Integrated circuit metal oxide semiconductor field effect transistors (MOSFETs) include silicon germanium (Si
1-x
Ge
x
) channels have been widely reported. A thin silicon cap layer usually is deposited on the SiGe layer. This silicon cap acts to prevent the diffusion of germanium into the silicon dioxide gate dielectric material, separates the hole channel from the gate dielectric in strained SiGe p-type metal oxide semiconductor field effect transistors (pMOSFETs), and forms a high-mobility electron or hole channel in strained-Si MOSFETs.
In enhanced mobility MOSFET device applications, thick, relaxed Si
1-x
Ge
x
buffer layers have been used as virtual substrates for thin, tensile-strained Si layers to increase carrier mobility for both NMOS and PMOS devices. Compared with bulk Si devices, enhancement in electron mobility of 70% for devices with an effective length less than 70 nanometers (nm) has been reported. Enhancements of up to 40% in high-field hole mobility for long-channel devices have also been found. The most popular, current technique to produce a high quality relaxed Si
1-x
Ge
x
buffer layer is the growth of a several micrometers thick compositionally graded layer. Alternatively, both Helium and Hydrogen implantation followed by annealing have been reported as methods to improve the efficiency of relaxation.
Yet another device structure includes growing a thin, strained SiGe layer followed by a thin, relaxed Si layer. This structure improves PMOS mobilities, but does not help NMOS.
Regardless of the thickness or strained/unstrained state of the individual layers of these prior art devices, a disadvantage of each these prior art processes is that the device is subjected to high temperature processing after formation of the silicon cap layer. In other words, regardless of whether the SiGe is thick or thin, strained or relaxed, it is critical to minimize the diffusion of Ge into the overlying Si cap/channel during subsequent process steps. In particular, during the subsequent gate oxidation, the gate polysilicon deposition and the dopant activation, there invariably will be diffusion of the germanium into the silicon dioxide gate dielectric material. This diffusion of germanium into the gate dielectric material causes degradation of device performance.
Accordingly, there is a need for a device and a method of fabricating the same wherein diffusion of germanium into the gate dielectric is reduced or eliminated.
SUMMARY OF THE INVENTION
The present invention provides a device and a method of fabricating the same, wherein the method comprises combining the use of a deposited gate dielectric and a metal gate in a gate replacement process within the SiGe channel. Because the gate dielectric is deposited after all of the high temperature treatments on the device, there is negligible diffusion of the germanium into the gate dielectric material.
Accordingly, an object of the invention is to provide an integrated circuit metal oxide semiconductor device having reduced germanium in the gate dielectric material.
Another object of the invention is to provide a method of fabricating an integrated circuit metal oxide semiconductor device having reduced germanium in the gate dielectric material.
A further object of the invention is to provide a method of fabricating an integrated circuit metal oxide semiconductor device having reduced germanium in the gate dielectric material wherein the gate dielectric material is deposited after the device has undergone all of the high temperature treatments.


REFERENCES:
patent: 6310367 (2001-10-01), Yagishita et al.
patent: 6313486 (2001-11-01), Kencke et al.

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