Integrated circuit memory with variable addressing of memory cel

Details Integrated circuit memory with variable addressing of memory cel Integrated circuit memory with variable addressing of memory cel

1992-07-15

1994-11-08

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518912, 365239, 365240, G11C 800

Patent

active

053633377

ABSTRACT:
An integrated circuit memory array has a data input/output, a Read/Write* signal input, a row decoder, and a column decoder. An input circuit inputs a beginning and ending address to an on-chip memory controller which then sequentially addresses the beginning address, all the cells between the beginning address and the ending address, and the ending address, causing the array to sequentially output or input data from the sequence of cells, depending on the state of the Read/Write* signal.

REFERENCES:
patent: 4675808 (1987-06-01), Grinn et al.
patent: 4773049 (1988-09-01), Takemae
patent: 4845678 (1989-07-01), Van Berkel et al.
patent: 5021951 (1991-06-01), Baba
patent: 5235545 (1993-08-01), McLaury

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