Integrated circuit memory with non-binary array configuration

Details Integrated circuit memory with non-binary array configuration Integrated circuit memory with non-binary array configuration

1991-10-25

1993-06-15

Dixon, Joseph L.

Static information storage and retrieval

Format or disposition of elements

365200, 36523003, 36523006, G11C 502, G11C 800

Patent

active

052205185

ABSTRACT:
Memory arrays of non-binary physical dimensions are disclosed. A novel addressing scheme provides that multiple word lines are activated in response to each received address code. Generally, at least two physical block rows containing blocks of an addressed logical block row are activated in response to each address. Block rows containing redundant blocks are activated in response to every address. In a specific embodiment, a 1 M-bit array arranged in 11 rows of blocks and 6 columns of blocks functions as an 8.times.8 block logical array, with two blocks available for redundancy. The availablity of non-binary physical arrays affords a designer new flexibility in meeting packaging constraints and redundancy specifications.

REFERENCES:
patent: 3906458 (1975-09-01), Ehlers
patent: 4047163 (1977-09-01), Choate et al.
patent: 4791607 (1988-12-01), Igarashi et al.
patent: 4811297 (1989-03-01), Ogawa
patent: 4918662 (1990-04-01), Kondo
patent: 4945513 (1990-07-01), Ueda
patent: 5093805 (1992-03-01), Singh

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