Integrated circuit memory with decoded address sustain circuitry

Details Integrated circuit memory with decoded address sustain circuitry Integrated circuit memory with decoded address sustain circuitry

1991-04-02

1993-09-14

Callahan, Timothy P.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523002, 307449, 307463, G11C 11407

Patent

active

052455831

ABSTRACT:
An integrated circuit memory device is provided which includes a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of y-lines; an address bus including a first bus oriented with a y-dimension and a second bus oriented with an x-dimension; and x-address generator; a y-address generator; a multiplexer circuit for operatively coupling one of the x-address generator and the y-address generator to the address bus; a plurality of y-address decoders each for producing decoded y-information to at least one of the plurality of y-lines; a plurality of separate x-address decoders each for producing decoded x-information for at least one of the plurality of x-lines; and a plurality of separate sustain circuits each for sustaining decoded x-information produced by at least one x-decoder.

REFERENCES:
patent: 5027008 (1991-06-01), Runaldue
patent: 5051959 (1991-09-01), Nakano et al.

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