Integrated circuit memory with asymmetric row access topology

Details Integrated circuit memory with asymmetric row access topology Integrated circuit memory with asymmetric row access topology

1992-08-18

1994-05-10

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518901, 365206, 365221, G11C 700

Patent

active

053114787

ABSTRACT:
A DRAM or VRAM integrated circuit memory of the divided bit line design includes a first bit line pair divided into a first pair of bit line halves and a second pair of bit line halves, and second bit line pair divided into a third pair of bit line halves and a fourth pair of bit line halves. A row decoder addresses a row associated with the first pair of bit line halves during a first time period, addresses a row associated with the second pair of bit line halves in a second time period, addresses a row associated with the third pair of bit line halves in the first time period, and addresses a row associated with the fourth pair of bit line halves in the second time period. The access topology is thus asymmetric with respect to a column decoder connected to the second and third pairs of bit line halves.

REFERENCES:
patent: 4636987 (1987-01-01), Norwood et al.
patent: 5018110 (1991-05-01), Sugiyama et al.
patent: 5053997 (1991-10-01), Miyamato et al.

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