Integrated circuit memory having divided-well architecture

Details Integrated circuit memory having divided-well architecture Integrated circuit memory having divided-well architecture

1999-08-04

2001-02-13

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270

Reexamination Certificate

active

06188607

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit having memory cells.
2. Description of the Related Art
Electrically programmable read-only memories (EEPROMs) are used in a variety of applications where non-volatile memory operation is desired. In particular, the so-called “flash” EEPROM has gained favor in recent years due to the ease of erasing an entire array of information at one time, which reduces the time required to re-program the information in the memory. In particular, secondary electron injection has been invented by J. Bude et al as a low power and scaleable programming method for flash EEPROM memory; see, for example, U.S. Pat. No. 5,659,504 co-assigned herewith and incorporated herein by reference.
An illustrative EEPROM according to the teachings of that patent is depicted in FIG.
1
. The EEPROM in
FIG. 1
has the stacked gate structure of a double-polysilicon MOSFET (metal-oxide-semiconductor field effect transistor). The EEPROM in
FIG. 1
has a semiconductor region
100
, source region
110
, drain region
120
, channel
130
, floating gate
140
, and control gate
160
found in conventional EEPROMs. The floating gate
140
is a layer of polysilicon isolated from the semiconductor region
100
and the control gate
160
by a first layer of silicon dioxide
150
and a second layer of silicon dioxide
170
, respectively. The first layer of silicon dioxide
150
is sufficiently thin, i.e. about 100 Angstroms or less, for electrons to pass therethrough by either Fowler-Nordheim (FN) tunneling or by hot electron injection. The semiconductor region
100
is typically a tub region of a given conductivity type formed in an underlying doped region (not shown), typically another tub of the opposite dopant type, formed in an underlying wafer substrate (also not shown) of the given conductivity type. Other details of operation and embodiments may be found in the above-noted patent.
An array of memory cells is arranged in rows and columns, with the rows typically viewed horizontally and the columns vertically. A row conductor is usually referred to as a “word line”, and activates the memory cell for storing (i.e., writing) or retrieving (i.e., reading) information to or from the cell. In a typical case, the word line is connected to the gate of a field effect transistor, which device may itself provide for storing the information, or may provide access to another device used for storing information. The column conductor is usually referred to as a “bit line”, and typically connects to the drain of a field effect transistor for transferring electrical charge into the storage element (i.e., writing), or retrieving charge from the storage element (i.e., reading), after the transistor is accessed by the word line. Comparable connections are made when bipolar memory devices are used rather than field effect devices.
Because the devices of the above-noted U.S. patent utilize the drain-tub bias to affect electron injection into the tub, the devices can be selectively enabled or disabled by varying the tub voltage to a device or a particular sub-array of devices. For example, in an array of EEPROM cells depicted in FIG. 6 of that patent, the array is divided into two sub-arrays. The tub connections to a particular sub-array are commonly connected to a sub-array select line. The sub-array select lines are isolated from each other and consequently, the tub voltage in one sub-array is capable of being modulated differently from the tub voltage in other sub-array. The devices of the above-noted patent may be programmed only when the tub voltage is −0.5 V or more negative. Therefore, a cell in a particular sub-array can be deselected by raising the tub voltage to the sub-array (i.e., make it more positive with respect to the substrate) in which the cell to be deselected is found. Further details of operation may be found in the above-noted patent. However, note that the sub-arrays share common word lines that run from one sub-array to another. For the purpose of selecting and deselecting along the bit line direction, different word line biases are sufficient.
The “bit line disturb” of a memory cell refers to the disturbance of non-accessed memory cells along a given bit line when one of the cells on the bit line is accessed for a write operation. In particular, non-volatile memory cells should have as large a margin against bit line disturb as possible, since the information is typically not refreshed in the cell, and may need to be maintained for lengthy periods. Recent test results have shown that the bit line disturb margin of EEPROM cells that use secondary electron programming is less than that of EEPROM cells using conventional channel hot-electron injection. Existing methods to reduce bit line disturb include organizing a big array into many smaller separated sub-arrays or making use of divided-bit line architecture, but in both ways the required additional decoding adds considerable amount of complexity and area to the memory array.
SUMMARY OF THE INVENTION
I have invented an integrated circuit having a memory array comprising memory devices formed in a multiplicity of electrically isolated semiconductor regions that share a common set of bit lines. A given semiconductor region, typically a tub, is biased to a given voltage if a memory cell formed in that tub is accessed for a write operation, and biased to another voltage at other times. The present technique is especially advantageous when used with flash EEPROM memory cells that utilize secondary electron injection to assist in programming the cells.


REFERENCES:
patent: 4878199 (1989-10-01), Mitzutani
patent: 6025621 (2000-02-01), Lee et al.

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