Static information storage and retrieval – Addressing – Sync/clocking
Patent
1995-02-24
1996-08-13
Nguyen, Viet Q.
Static information storage and retrieval
Addressing
Sync/clocking
365191, 365194, 36518901, G11C 700
Patent
active
055463550
ABSTRACT:
An integrated circuit memory (20) has a write pulse generator (38) for generating a self-timed write pulse independent of system clock frequency and system clock duty cycle. The write pulse generator (38) includes a delay element (56) and a delay element (68). The write pulse is triggered on a rising edge of the clock signal and has a duration that is determined by a delay time provided by the delay element (68). The delay elements (56, 68) provide single-sided delays and compensate for process, power supply, temperature variations of the integrated circuit memory (20).
REFERENCES:
patent: 5227671 (1993-07-01), Ehrlich
patent: 5440514 (1995-08-01), Flannagan et al.
Feng Taisheng
Raatz Donovan L.
Hill Daniel D.
Motorola Inc.
Nguyen Viet Q.
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